Featured post

Top 5 books to refer for a VHDL beginner

VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Sunday 9 September 2012

Range Specification

Formal Definition

The range specification can be used to specify an array of gate or module instances.

Simplified Syntax

instance_name[l_index:r_index] (list of terminals);


The range should be specified using two constant expressions separated by a colon and bracketed by square brackets. The expressions constitutes: the left-hand index (l_index) and right-hand index (r_index). The left-hand index can be less than, equal, or greater than the right-hand index (Example 1). If these indexes are equal then only one instance will be generated (Example 2). Identical instance names cannot appear twice with other range specifications (even if ranges do not overlap each other).


Example 1

reg [3:0] a, b;
wire [3:0] y;
and g[3:0](y,a,b);

This declaration is equivalent to:

and g3 (y[3], a[3], b[3]);
and g2 (y[2], a[2], b[2]);
and g1 (y[1], a[1], b[1]);
and g0 (y[0], a[0], b[0]);

Example 2

reg a, b;
wire y;
or g[0:0](y,a,b);

This declaration is equivalent to:
or g (y, a, b);

Important Notes

· If the range is used in module or gate instantiations, then terminals of all output ports should not be scalars or there may be a bus conflict.

No comments:

Post a Comment

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.