VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
Wednesday, 17 March 2010
Tuesday, 16 March 2010
Netgen version 1.3 is the stable branch and has been essentially unchanged for several years. The development branch version 1.4 is an attempt to bring netgen up to par with the industry-standard Calibre tool from Mentor Graphics. Since (as far as I know) all LVS tools are based on the same class partitioning algorithm, this effort is not as difficult as it may seem. Mostly, netgen must be made to properly understand hierarchy, device properties, and generate a more readable output. All these changes are now underway (as of November 2007, when the development version 1.4 branch was created).
Netgen was developed independently of magic, written by Massimo Sivilotti, and eventually incorporated into the beginnings of the Tanner L-Edit suite of tools. However, the original code was left open source, and so I have incorporated it into the Tcl-based suite of tools including magic, IRSIM, and xcircuit.
IRSIM shares a history with magic, although it is an independent program. Magic was designed to produce, and IRSIM to read, the ".sim" file format, which is largely unused outside of these two programs. IRSIM was developed at Stanford, while Magic was developed at Berkeley. Parts of Magic were developed especially for use with IRSIM, allowing IRSIM to run a simulation in the "background" (i.e., a forked process communicating through a pipe), while displaying information about the values of signals directly on the VLSI layout.
For "quick" simulations of digital circuits, IRSIM is still quite useful for confirming basic operation of digital circuit layouts. The addition of scheduling commands ("at", "every", "when", and "whenever") put IRSIM into the same class as Verilog simulators. It is, in my opinion, much easier to write complicated testbench simulations using Tcl and IRSIM. I have used IRSIM to validate the digital parts of several production chips at MultiGiG, including the simulation of analog behavior such as PLL locking.
IRSIM version 9.5 was a long-standing and stable version that corresponded to the relatively stable Magic version 6.5. When magic was recast in a Tcl/Tk interpreter framework (versions 7.2 and 7.3), IRSIM could no longer operate as a background process. However, it was clear that if IRSIM could also be recast in the same Tcl/Tk interpreter framework, the level of interaction between it and Magic would be greatly increased.
I set about to create the "new" IRSIM, although it came along in fits and starts as I had time to work on it. Because the original "analyzer" graphic display window (and GUI, to a very limited extent) was written in Xt (the rather primitive window system that is an integral part of X11), it was scrapped for a while. In its place, I substituted graphs in "Blt" based on the same in "tclspice" (see SourceForge for the tclspice project). Unfortunately, "Blt" insists that all data vectors must be real-valued, which is 1) a severe waste of space for binary digital values, and 2) is unable to represent the concept of an "unknown" value that is so crucial to fast switch simulation. So, eventually I was forced to scrap BLT and actually sit down and code out a real Tcl-based analyzer window and GUI. The result is finally done in revision 9.7.3.
XCircuit is a UNIX/X11 (and Windows, if you have an X-Server running, or Windows API, if not) program for drawing publishable-quality electrical circuit schematic diagrams and related figures, and produce circuit netlists through schematic capture. XCircuit regards circuits as inherently hierarchical, and writes both hierarchical PostScript output and hierarchical SPICE netlists. Circuit components are saved in and retrieved from libraries which are fully editable. XCircuit does not separate artistic expression from circuit drawing; it maintains flexiblity in style without compromising the power of schematic capture.
- HDL Editor
- StateCAD State Machine Editor
- Schematic Editor - Engineering Capture System (ECS)
- CORE Generator
- XST - Xilinx Synthesis Technology
- Integration with LeonardoSpectrum from Mentor Graphics, Inc.
- Integration with Synplify from Synplicity, Inc.
- HDL Bencher Testbench Generator
- Integration with ModelSim Simulator from Model Technology, Inc.
- Place and Route (PAR)
- FPGA Editor
- Timing Analyzer
- Fit (CPLD only)
- Chipviewer (CPLD only)
Device Download and Program File Formatting
Download the Xilinx ISE 10.1 design suit from Here
Saturday, 13 March 2010
Thursday, 4 March 2010
The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:
- Custom IC Layout
- Schematic Capture (Digital and Analog)
- Textual Languages such as VHDL and Verilog
- ....and much more.
The Electric VLSI Design System is a highly flexible and powerful system that can handle many different types of circuit design (MOS, Bipolar, schematics, printed circuitry, hardware description languages, etc.) It handles geometry at any angle (not just Manhattan) and can even handle curves.
Layout is done by placing and wiring electrical components. Although this is standard practice for schematics, it is unusual for chip layout. However, because of this style of design, Electric understands chip layout at a more sophisticated level, and can aid in design to an unprecedented degree.
Electric has many analysis tools, including design-rule checking, simulation, and network comparison. Electric has many synthesis tools, including routing, compaction, silicon compilation, PLA generation, and compensation.
The user interface is quite sophisticated and runs on all popular workstations (Windows, Macintosh, and UNIX). It also provides interpretive languages for advanced users.
The software is freely available at www.staticfreesoft.com
- what is the difference between mealy and moore state-machines
- how to solve setup and hold violations in the design
- what is antenna violation & ways to prevent it
- we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
- what is tie-high and tie-low cells and where it is used
- what is the difference between latches and flip-flops based designs
- what is High-Vt and Low Vt cells
- what is LEF mean?
- what is DEF mean?
- steps involved in designing an optimal padring
- what is metastability and steps to prevent it
- what is local-skew, global skew and useful skew
- what are the various timing-paths which i should take care in my STA runs?
- what are the various components of leakage-power
- what are the various yield losses in the design
- what is meant by virtual clock definition and why do i need it
- what are the various variations which impacts timing of the design
- what are the various Design constraints used, while performing synthesis for a design
- specify few verilog constructs which are not supported by the synthesis tool
- what are the various capacitances with an MOSFET?
- Vds-Ids curve for an MOSFET, with increasing Vgs
- explain basic operation of an MOSFET
- what is channel length modulation
- what is body effect
- what is latchup in CMOS design and ways to prevent it?
- what are the various design changes you do to meet design power targets
- what is meant by library characterization
- what is meant by wireload model
- what are the measures to be taken to design for optimized area
- what all will you be thinking while performing floorplan
- what are the measures in the design taken for meeting signal integrity targets
- what are the measures taken in the Design achieving better yield
- what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
- what are the steps incorporated for Engineering Change order[ECO]
- what are the steps performed to achieve Lithography friendly Design
- what does synthesis mean?
- what are the pre-requistes to perform synthesis
- can you explain the synthesis flow
- what are the various ways to reduce clock insertion delay in the design
- what are the various functional verification methodologies
- what does formal verification mean
- how will you time the output path in STA
- how will you time the input path in STA
- what is false path mean in STA and in what scenarios falsepath can come
- what does multicycle path mean in STA and in what scenarios MCP can come
- what are source synchronous paths in STA
- Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it.
- we have multiple instances in RTL, do you do anything special during synthesis stage
- what do you call an event and when do you call an assertion.
- what is difference between FPGA and ASIC.
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