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Top 5 books to refer for a VHDL beginner

VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Saturday 27 February 2010

A typical analog design flow

In case of analog design, the flow changes somewhat.

=>Specifications=> Architecture =>Circuit Design =>SPICE Simulation =>Layout =>Parametric Extraction / Back Annotation =>Final Design =>Tape Out to foundry.

While digital design is highly automated now, very small portion of analog design can be automated. There is a hardware description language called AHDL but is not widely used as it does not accurately give us the behavioral model of the circuit because of the complexity of the effects of parasitic on the analog behavior of the circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs. This is true for small transistor count chips such as an operational amplifier, or a filter or a power management chip. For more complex analog chips such as data converters, the design is done at a transistor level, building up to a cell level, then a block level and then integrated at a chip level. Not many CAD tools are available for analog design even today and thus analog design remains a difficult art. SPICE remains the most useful simulation tool for analog as well as digital design.

From above discussion n from my personal experience i feel that digital design is the most important aspect of the VLSI design flow. Think if your design has some bug...!! the whole process then is costing billions of $. So it's very essential to take care start from the initial phase of designing.

Here during our discussion further we will go through several important concepts of digital dsigning and also see some standard designs.

A typical digital design flow

Specification =>Architecture =>RTL Coding =>RTL Verification =>Synthesis =>Backend =>Tape Out to Foundry to get end product….a wafer with repeated number of identical Ics.

All modern digital designs start with a designer writing a hardware description of the IC (using HDL or Hardware Description Language) in Verilog/VHDL. A Verilog or VHDL program essentially describes the hardware (logic gates, Flip-Flops, counters etc) and the interconnect of the circuit blocks and the functionality. Various CAD tools are available to synthesize a circuit based on the HDL. The most widely used synthesis tools come from two CAD companies, Synposys and Cadence.

Without going into details, we can say that the VHDL can be called as the "C" of the VLSI industry. VHDL stands for "VHSIC Hardware Definition Language", where VHSIC stands for "Very High Speed Integrated Circuit". This language is used to design the circuits at a high-level, in two ways. It can either be a behavioral description, which describes what the circuit is supposed to do, or a structural description, which describes what the circuit is made of. There are other languages for describing circuits, such as Verilog, which work in a similar fashion.

Both forms of description are then used to generate a very low-level description that actually spells out how all this is to be fabricated on the silicon chips. This will result in the manufacture of the intended IC.

Friday 26 February 2010


The de-multiplexer is the inverse of the multiplexer, in that it takes a single data input and n address inputs. It has 2n outputs. The address input determine which data output is going to have the same value as the data input. The other data outputs will have the value 0.


Just opposite to decoder an encoder has many inputs but less outputs.
Below figure shows an example of 4-to-2 Encoder 


A multiplexer performs the function of selecting the input on any one of 'n' input lines and feeding this input to one output line.

Assume that we have four lines, C0C1C2 and C3, which are to be multiplexed on a single line, Output (f). The four input lines are also known as the Data Inputs. Since there are four inputs, we will need two additional inputs to the multiplexer, known as the Select Inputs, to select which of the C inputs is to appear at the output. Call these select lines A and B.
The gate implementation of a 4-line to 1-line multiplexer is shown below:

Saturday 6 February 2010

Xilinx Virtex-6 FPGA Family Achieves Full Production Qualification on UMC’s High-Performance 40nm

UMC, a leading global semiconductor foundry, and Xilinx Inc. (XLNX) today announced they have fully qualified the Virtex(R)-6 FPGA family on the foundry's high- performance 40nm logic process. The qualification is the result of the close work between engineering teams from both companies to further enhance yield, reliability and cycle time. The full qualification of the Virtex-6 family signifies the transition to 40nm volume production following UMC's first shipments of the devices in March 2009.
"We highly value the ongoing execution of our long time manufacturing partner UMC," said Xilinx CEOMoshe Gavrielov. "We have collaborated together to deliver several generations of industry leading FPGA families."
"This 40nm achievement follows a long history of successful product family launches with Xilinx," said UMC CEO Dr. Shih-Wei Sun. "Today's production readiness of the 40nm Virtex-6 family underscores our ongoing commitment to Xilinx and our long-term partnership."
Built using third-generation Xilinx ASMBL(TM) architecture, the Virtex-6 FPGA family delivers 15% higher performance and 15% lower power consumption compared to competitive 40nm FPGA offerings. The devices operate on a 1.0v core voltage with an available 0.9v low-power option and are supported by a new generation of development tools delivered by ISE(R) Design Suite 11 and a vast library of IP already available for the market leading 65-nm Virtex-5 FPGA family to ensure productive development and design migration.
"Reaching the production milestone means we have stable and predictable yields that allow us to meet our growing customer demands reliably," said Vincent Tong, Xilinx Senior Vice President, New Product Introductions and Worldwide Quality. "This would not be possible without the joint collaboration with UMC where we used Xilinx's next generation FPGA diagnostic tools along with UMC's rapid info-turn yield learning vehicles to achieve significant yield and quality improvement of 40nm."
Early engagement, design for manufacturing and an effective test vehicle process are also contributing to the successful roll-out of the Virtex-6 family. By building on what they learned from working together closely on previous generations, the Xilinx and UMC engineering teams were able to beat the tape-out to production duration of the Virtex-5 family by a quarter, Tong noted.
"The successful qualification of Virtex-6 is the result of the close teamwork between Xilinx and UMC engineers to address the challenges of 40nm high performance technology," said S.C. Chien, Vice President of Advanced Technology Development at UMC. "UMC dedicated significant engineering talent and resources in our joint effort with Xilinx, such as customizing device specifications to their product specifications, delivering DFM for stable yield, fast info-turn vehicle to enhance quality, and quick diagnosis methodology. We are excited to see that our teamwork has paid off with today's milestone."
UMC's independently developed 45/40nm logic process utilizes sophisticated immersion lithography for its 12 critical layers and incorporates the latest technology advancements such as ultra-shallow junction, embedded silicon- germanium and mobility enhancement techniques, and ultra low-k dielectrics. Currently, several customers have 45/40nm products being manufactured at UMC, with thousands of wafers having already been shipped.
Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. The Virtex-6 FPGA family comprises three domain-optimized FPGA platforms that deliver different feature mixes, including DSP slices, memory blocks and serial transceivers supporting up to 11.2Gb/s to best address a variety of customer applications. Currently, six out of nine Virtex-6 family base devices are shipping. All nine are scheduled to be available in production volumes by the end of the second quarter of CY2010.
About UMC
UMC ( UMC, TSE: 2303) is a leading global semiconductor foundry that provides advanced technology and manufacturing services for applications spanning every major sector of the IC industry. UMC's customer-driven foundry solutions allow chip designers to leverage the strength of the company's leading-edge processes, which include production proven 65nm, 45/40nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 12,000 people worldwide and has offices in TaiwanJapanSingaporeEurope, and the United States. UMC can be found on the web athttp://www.umc.com .
About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visithttp://www.xilinx.com/ .
XILINX, the Xilinx Logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Tuesday 2 February 2010


Decoder is a multiple input; multiple output logic circuit that converts coded inputs in coded outputs, where input and output codes are different.

Inputs have fewer inputs than output. Below is a simple example of 2-to-4 decoder.