VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
Tuesday, 15 June 2021
Monday, 7 June 2021
One of our colleagues always had to struggle with the Verilog / SystemVerilog syntax. Whenever he opens a .sv file he needs to set the syntax manually as ":set syntax=verilog". This really kills time, especially when you are working on a project with tight schedules.
Opening a fine using GVIM
Shortcuts for moving the cursor:
Shortcuts for quick editing:
How do I switch between panes in a split mode in Vim/GVIM ??
How to remove blank lines from a file?
How to implement AUTO-COMPLETION
Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verification Methodology) is a standardized methodology for verify...
This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage. ...
Q11: Difference between module & class based TB? Ans: A module is a static object present always during of the simulation. A Cl...
Q26: What is p_sequencer ? OR Difference between m_sequencer and p_sequencer? m_sequencer is the default handle for uvm_vitual_sequenc...
Q16: Is uvm is independent of systemverilog ? Ans: UVM is a methodology based on SystemVerilog language and is not a language on its own...