VLSI FPGA Projects Topics Using VHDL/Verilog

    1. 8-bit Micro Processor

    2. RISC Processor in VLDH

    3. Floating Point Unit

    4. LFSR - Random Number Generator

    5. Versatile Counter

    6. RS232 interface

    7. I2C Slave

    8. 8b10b Encoder/Decoder

    9. Floating Point Adder and Multiplier

    10. Progressive Coding For Wavelet-Based Image Compression

    11. An Area-Efficient Universal Cryptography Processor for Smart Cards

    12. FPGA Based Power Efficient Channelizer for Software Defined Radio

    13. Implementation of IEEE 802.11a WLAN baseband Processor using FPGA with Verilog/VHDL code

    14. FPGA Implementation of USB Transceiver Macrocell Interface with Usb2.0 Specifications

    15. Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFIC

    16. Superscalar Power Efficient Fast Fourier Transform FFT Architecture

    17. High-Speed Architecture for Reed-Solomon Decoder/Encoder

    18. Fault Secure Encoder and Decoder for Nano-memory Applications

    19. Implementation Huffman Coding For Bit Stream Compression In Mpeg – 2

    20. Implementation of Hash Algorithm Used for Cryptography And Security

    21. Implementation of Scramblers and Descramblers in Fiber Optic Communication Systems – SONET and OTN

    22. Implementation of Matched Filters Frequency Spectrum in Code Division Multiple Access (CDMA) System and its Implementation

    23. High Definition HDTV Data Encoding and Decoding using Reed Solomon Code

    24. Design & Implementation of Noise / Echo canceler using FPGA with Verilog/VHDL

    25. A VLSI Architecture for Visible Watermarking In A Secure Still Digital Camera (S2dc) Design

    26. FPGA-Based Architecture for Real Time Image Feature Extraction

    27. Implementation of Lossless Data Compression and Decompression using (Parallel Dictionary Lempel Ziv Welch) PDLZW Algorithm

    28. 8/16/32 Point Fast Fourier Transform Algorithm using FPGA with Verilog/VHDL

    29. VLSI Implementation of Booths Algorithm using FPGA with Verilog/VHDL

    30. Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFICs

    31. VLSI implementation of Cascaded-Integrator-Comb Filter

    32. VLSI implementation of Wave-Digital-Filters

    33. VLSI implementation of Notch filters

    34. VLSI implementation of fractional sample rate converter (FSRC) and corresponding converter architecture

    35. VLSI implementation of canonical Huffman encoder/decoder algorithm using FPGA with Verilog/VHDL code

    36. VLSI implementation of RC5 Encryption/Decryption Algorithm

    37. VLSI implementation of Steganography using FPGA with Verilog/VHDL code

    38. VLSI implementation of 16 Bit fixed point DSP Processor using FPGA with Verilog/VHDL

    39. VLSI Implementation of Address Generation Coprocessor

    40. VLSI Implementation of AHDB (Adaptive Huffman Dynamic Block) Algorithm

    41. Implementation of LZW Data Compression Algorithm.

    42. A Low Power VLSI Implementation for JPEG2000 Codec using FPGA with Verilog/VHDL

    43. A Verilog Implementation of Built In Self Test of UART

    44. Fuzzy based PID Controller using VHDL for Transportation Application

    45. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication

    46. Scalable multi gigabit pattern matching for packet inspection

    47. An FPGA-based Architecture for Real Time Image Feature Extraction

    48. Synchronization in Software Radios – Carrier and Timing Recovery Using FPGAs

    49. Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

    50. High-Speed Booth Algorithm Encoded Parallel Multiplier Design

    51. Implementation of IEEE 802.11a WLAN Baseband Processor

    52. MPEG-4 AVClH.264 Transform Coding Design using FPGA with Verilog/VHDL

    53. FPGA based Generation of High Frequency Carrier for Pulse Compression using CORDIC Algorithm

    54. Watermarking in a Secure Still Digital Camera Design

    55. DCT/IDCT Algorithms Implemented in FPGA Chips for Real-Time Image Compression

    56. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication

    57. Robust Image Watermarking Based on Multiband Wavelets and Empirical Mode Decomposition

    58. A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design

    59. VLSI Design & Implementation of Cryptography AES/DES Encryption Algorithm using FPGA with Verilog/VHDL code

    60. VLSI Design & Implementation of Viterbi Algorithm-Encoder/Decoder using FPGA with Verilog/VHDL code

    61. VLSI Design & Implementation of DDRR Algorithm using FPGA with Verilog/VHDL code

    62. VLSI Design & Implementation of Dynamic/Deficit Round Robin Algorithm using FPGA with Verilog/VHDL code

    63. VLSI Design & Implementation of Watermarking Algorithm using FPGA with Verilog/VHDL code

    64. VLSI Design & Implementation of Secure transmitting and receiving text data in communication systems using FPGA with Verilog/VHDL code

    65. VLSI Design & Implementation of UART Asynchronous Transmitter/Receiver using FPGA with Verilog/VHDL code

    66. VLSI Design & Implementation of RS-232 Transmitter/Receiver using FPGA with Verilog/VHDL code

    67. VLSI Design & Implementation of Asynchronous Serial controller using FPGA with Verilog/VHDL code

    68. VLSI Design & Implementation of Universal Serial Bus USB Device Controller using FPGA with Verilog/VHDL code

    69. VLSI Design & Implementation of GPS-GSM based Home Automation System using FPGA with Verilog/VHDL code

    70. VLSI Design & Implementation of 16/32/64-bit Low Power RISC/CISC Processor using FPGA with Verilog/VHDL code

    71. VLSI Design & Implementation of Multichannel I2S Audio Controller using FPGA with Verilog/VHDL code

    72. VLSI Design & Implementation of Asynchronous FIFO using FPGA with Verilog/VHDL code

    73. VLSI Design & Implementation of AHB Master/Slave using FPGA with Verilog/VHDL code

    74. VLSI Design & Implementation of AMBA AHB to PVCI Bridge using FPGA with Verilog/VHDL code

    75. VLSI Design & Implementation of Huffman Encoder/Decoder using FPGA with Verilog/VHDL code

    76. VLSI Design & Implementation of Programmable 16-Tap FIR Filter using FPGA with Verilog/VHDL code

    77. VLSI Design & Implementation of 2-D Convolution Engine using FPGA with Verilog/VHDL code

    78. VLSI Design & Implementation of VGA/LCD Controller using FPGA with Verilog/VHDL code

    79. VLSI Design & Implementation of JTAG TAP controller using FPGA with Verilog/VHDL code

    80. VLSI Design & Implementation of Booth Multiplier using FPGA with Verilog/VHDL code

    81. VLSI Design & Implementation of Pipeline JPEG Encoder using FPGA with Verilog/VHDL code

    82. VLSI Design & Implementation of Cyclic Redundancy Check ECRC/LCRC Error Check using FPGA with Verilog/VHDL code

    83. VLSI Design & Implementation of Vehicle Tracking & Safety System using FPGA with Verilog/VHDL code

    84. VLSI Design & Implementation of Low Power FIR Filter using FPGA with Verilog/VHDL code

    85. VLSI Design & Implementation of Pattern Generator using FPGA with Verilog/VHDL code

    86. VLSI Design & Implementation of PCI Express using FPGA with Verilog/VHDL code

    87. VLSI Design & Implementation of Highspeed USB 2.0/Superspeed USB 3.0 Transmitter and Receiver using FPGA with Verilog/VHDL code

    88. VLSI Design & Implementation of Wishbone Controller using FPGA with Verilog/VHDL code

    89. VLSI Design & Implementation of PVCI Master/Slave using FPGA with Verilog/VHDL code

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4 comments:

  1. Hi there, awesome site. I thought the topics you posted on were very interesting. I tried to add your RSS

    to my feed reader and it a few. take a look at it, hopefully I can add you and follow.

    Projects in VLSI

    ReplyDelete
  2. Thanks Steffi... :)

    you can find feeds @
    http://feeds.feedburner.com/VlsiEncyclopedia

    ReplyDelete
  3. These are really nice projects .... thanks :)

    ReplyDelete
  4. please suggest me how to implement a USB device controller in fpga with verilog code

    ReplyDelete

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