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Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Saturday, 9 July 2011

Intel’s Haswell Microarchitecture

Haswell is the codename for a processor microarchitecture to be developed by Intel's Oregon team as successor to the Sandy Bridge architecture.Haswell will use a 22 nm process.CPUs based on the Haswell microarchitecture are expected to be released in 2013. There are currently no details regarding this microarchitecture's development.

Haswell is confirmed to have:

  • A 22 nm process.
  • 3D tri-gate transistors.
  • Advanced Vector Extensions 2(AVX2) instruction set (or Haswell New Instructions)

Haswell is expected to have:

  • FMA3 instructions.
  • A 14 stage pipeline.
  • A new cache design.
  • Up to 8 cores available.
  • New advanced power-saving system.
  • 64 kB data + 64 kB instruction L1 cache per core, 8-way associativity
  • 1 MB L2 cache per core, 8-way associativity.
  • Up to 32 MB L3 cache shared by all cores, 16-way associativity.

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