Featured post

Top 5 books to refer for a VHDL beginner

VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Thursday 30 June 2011

Clock Skew In Sequential Circuits

Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design principle that timing must satisfy register setup and hold time requirements. Both data propagation delay and clock skew are parts of these calculations. Clocking sequentially-adjacent registers on the same edge of a high-skew clock can potentially cause timing violations or even functional failures.

Below Figure 1 shows an example of sequentially-adjacent registers, where a local routing resource has been used to route the clock signal. In this situation, a noticeable clock skew is likely.

In Figure 1, all registers are clocked at the same edge, but the arrival time of the edge is different at each register. Figure 2 indicates an example of the clock skew for the circuit shown in Figure 1.

Clock_skew_in_registerFigure 1: Sequentially Adjacent Registers with Clock Skew

Clock_skew_timing_diagramFigure 2: Clock Arrival Time Functions in the Circuit of Figure 1

No comments:

Post a Comment

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.