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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Sunday 23 December 2012


Formal Definition

A package declaration defines the interface to a package.

Simplified Syntax

package package_name is


end package package_name;


The package is a unit that groups various declarations, which can be shared among several designs. Packages are stored in libraries for greater convenience. A package consists of package declaration (mandatory) and may contain a single optional package body.

The purpose of a package is to declare shareable types, subtypes, constants, signals, files, aliases, component, attributes and groups. Once a package is defined, it can be used in multiple independent designs.

Items declared in a package declaration are visible in other design units if the use clause is applied (Example 1).

The two-part specification of a package (declaration and body) allows to declare the so-called deferred constants which have no value assigned in the package declaration (Example 2). The value for a deferred constant, however, must be declared in the package body accompanying the package declaration.

The VHDL Language Standard defines two standard packages, which must be available in any VHDL environment - package STANDARD and package TEXTIO. The former contains basic declarations of types, constants and operators, while the latter defines operations for manipulating text files. Both are located in the library STD. See respective topics for details.

Apart from the VHDL Language Standard there is another standard, which extends the language and supports the extensions in the form of a package: Std_Logic_1164.


Example 1

library Packages;
use Packages.AUXILIARY.all;
architecture STRUCT of Adder is
end architecture STRUCT;

All declarations, which are inside the AUXILIARY package, may be used in the architecture body STRUCT of the design entity Adder. The package itself is stored in the library Packages.

Example 2

library IEEE;
use IEEE.STD_LOGIC_1164.all;
package AUXILIARY is
type MUX_input is array (INTEGER range<>) of STD_LOGIC_VECTOR (0 to 7);
type operation_set is (SHIFT_LEFT, ADD);
subtype MUX_address is POSITIVE;
function Compute_Adress (IN1 : MUX_input) return MUX_address;
constant Deferred_Con : Integer;

Package AUXILIARY contains a function declaration and a deferred constant, thus a package body had to be declared for this package.

Important Notes

· Package declaration may contain a subprogram (function or procedure) declaration; subprogram body is not allowed here and must appear in the package body.

· Package body must accompany a package declaration if the declaration contains subprogram declarations or deferred constants.

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