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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Saturday 29 December 2012

Generate Statement

Formal Definition

A mechanism for iterative or conditional elaboration of a portion of a description.

Simplified Syntax

label : for parameter in range generate

[ { declarations }

begin ]

{ concurrent_statements }

end generate [ label ] ;

label : if condition generate

[ { declarations }

begin ]

{ concurrent_statements }

end generate [ label ] ;


The generate statement simplifies description of regular design structures. Usually it is used to specify a group of identical components using just one component specification and repeating it using the generate mechanism.

A generate statement consists of three main parts:

· generation scheme (either for scheme or if scheme);

· declarative part (local declarations of subprograms, types, signals, constants, components, attributes, configurations, files and groups);

· concurrent statements.

The generation scheme specifies how the concurrent structure statement should be generated. There are two generation schemes available: for scheme and if scheme.

The for generation scheme is used to describe regular structures in the design. In such a case, the generation parameter and its scope of values are generated in similar way as in the sequential loop statement. Example 1 illustrates this concept with N-bit binary counter created by the generate statement that instantiates N D-type flip-flops (Figure 1).


Fig. 1. The N-bit binary counter counting forward.

It is quite common that regular structures contain some irregularities. In such cases, the if scheme is very useful. Example 2 describes the synchronuous decimal counter that consists of JK flip-flops and NAND gates (Fig. 2). In that structure there are some irregularities related to the connection of the next level of flip-flops.


Fig. 2. The 8421 BCD counter counting forward.

A generate statement may contain any concurrent statement: process statement, block statement, concurrent assertion statement, concurrent procedure call statement, component instantiation statement, concurrent signal assignment statement, and another generate statement. The latter mechanism allows nesting the regular design structures and forming multidimensional arrays of components.


Example 1

entity D_FF is
port (D,CLK_S : in BIT;
      Q : out BIT := '0';
      NQ : out BIT := '1' );
end entity D_FF;
architecture A_RS_FF of D_FF is
BIN_P_RS_FF: process(CLK_S)
if CLK_S = '1' and CLK_S'Event
then Q <= D;
          NQ <= not D;
end if;
end process;
end architecture A_RS_FF;
entity COUNTER_BIN_N is
generic (N : Integer := 4);
port (Q : out Bit_Vector (0 to N-1);
      IN_1 : in Bit );
end entity COUNTER_BIN_N;
architecture BEH of COUNTER_BIN_N is
component D_FF
port(D, CLK_S : in BIT; Q, NQ : out BIT);
end component D_FF;
signal S : BIT_VECTOR(0 to N);
S(0) <= IN_1;
G_1 : for I in 0 to N-1 generate
D_Flip_Flop :
D_FF port map
(S(I+1), S(I), Q(I), S(I+1));
         end generate;
end architecture BEH;

First, a specification of a D flip-flop is given which will be used by the component declaration. The generate statement here is used to define a counter of arbitrary length, determined only by its generic parameter (set here to 4).

Example 2

-- the 8421 BCD counter
entity COUNTER_BCD is
port (IN_1 : in Bit; Q:out Bit_Vector(0 to 3));
end entity COUNTER_BCD;
architecture STRUCT of COUNTER_BCD is
component D_FF
port (J, K, CLK_S : in BIT; Q: out BIT);
end component D_FF;
component NAND_GATE
port (IN1, IN2 : in Bit; OUT1 : out Bit);
end component NAND_GATE;
signal S: Bit_vector(0 to 2);
signal L: Bit_vector(0 to 1);
D_FF_0 : D_FF port map ('1','1',IN_1, S(0));
Gen_1 : for I in 1 to 3 generate
Gen_2 : if I = 1 or I = 2 generate
D_FF_I : D_FF port map (S(I-1),S(I-1), IN_1, L(I-1));
NAND_I : NAND_GATE port map (S(I-1),L(I-1), S(I));
Q(I) <= L(I-1);
        end generate;
Gen_3 : if I = 3 generate
D_FF_3 : D_FF port map (S(I-1),S(I-1), IN_1, Q(I) );
          end generate;
   end generate;
Q(0) <= S(0);

Nested generate statements have been used here in order to shorten the description. The outmost generate statement specifies the complete counter, which component parts are generated by the inner statements depending on the index of the component (flip-flop) inside the counter.

Important Notes

· Each generate statement must have a label.

· If the generate statement does not contain any local declarations then the reserved word begin need not to be used.

· Generate statements can be nested.

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