It might be. If the code in question was written with no thought for how the FPGA would implement the circuit, then it's entirely possible that it was inefficient. If the code is written with consideration of the FPGA resources available and the synthesis tool being used, then no, it's not inefficient.
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Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
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Very often we come across questions from VLSI engineers that "Which scripting language should a VLSI engineer should learn?". Well...
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In previous post of this SystemVerilog Tutorial we talked about enumerated type in detail. Now we will look at the constants in SystemVe...
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This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage. ...
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In Verilog certain type of assignments or expression are scheduled for execution at the same time and order of their execution is not guara...
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