Because large parts of the language make no sense in a hardware context, synthesizable VHDL is a relatively small subset of VHDL. You must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular you must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure. Fundamentally, never forget that you are designing a circuit, not writing a program. Forgetting this simply but important fact will only lead to pain later.
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Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
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Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verification Methodology) is a standardized methodology for verify...
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This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage. ...
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Q11: Difference between module & class based TB? Ans: A module is a static object present always during of the simulation. A Cl...
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Q26: What is p_sequencer ? OR Difference between m_sequencer and p_sequencer? m_sequencer is the default handle for uvm_vitual_sequenc...
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Q16: Is uvm is independent of systemverilog ? Ans: UVM is a methodology based on SystemVerilog language and is not a language on its own...
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