Because large parts of the language make no sense in a hardware context, synthesizable VHDL is a relatively small subset of VHDL. You must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular you must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure. Fundamentally, never forget that you are designing a circuit, not writing a program. Forgetting this simply but important fact will only lead to pain later.
Subscribe to:
Post Comments (Atom)
-
This is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible comp... -
This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage. ...
-
Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verification Methodology) is a standardized methodology for verify... -
Very often we come across questions from VLSI engineers that "Which scripting language should a VLSI engineer should learn?". Well... -
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
No comments:
Post a Comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.