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Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Friday, 25 November 2011

Can you give me a measure of the productivity improvements I should expect from VHDL?

Well, do you believe the hype! Yes, ultimately there are considerable productivity gains to be had from using high-level design techniques in conjunction with synthesis technology, providing that your designs are: complex, amenable to synthesis, not dependent upon the benefits of a particular technology.

Obviously, complex means different things to different people, but a good rule of thumb is that complex means the implementation part of the design process is considerably more awkward than the specification phase. Let's face it, if the specification phase is significantly longer than the implementation phase, you need to put effort here, not into HLD. Of course, once you are benefiting from HLD productivity gains, the specification phase becomes more significant. OK, that's HLD: VHDL is a HLD design entry language, so we would expect the use of VHDL with synthesis technology to improve productivity in the design process. However, you won't get those benefits immediately. Your first VHDL-based project will probably take slightly longer than if you had used your previous design process.

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