Featured post

Top 5 books to refer for a VHDL beginner

VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...


UVM Guide for Beginners

Due to increasing trend of UVM for verification, we have created a guide that will assist a novice in building a verification environment using this methodology. We will not focus on verification techniques nor in the best practices in verifying a digital design, this guide was thought in helping you to understand the UVM API and in helping you to successfully compile a complete environment.
The simulator used is Mentor's Questasim but the testbench should compile in any HDL simulator that supports SystemVerilog.

  1. UVM Introduction
  2. Chapter - 1 The DUT
  3. Chapter - 2 Defining The Verification Environment
  4. Chapter - 3 Top Block
  5. Chapter - 4 Sequences And Sequencer


  1. Hi..
    Is this section incomplete? Talks of chapters 5 onwards, but there are no links?

  2. Hi..

    what is the difference between config_db and resourse_db ?

    1. Hi Ram,
      Please refer question #12 in below link


Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.