tag:blogger.com,1999:blog-49782373144522702272024-03-08T03:31:06.846-08:00Very Large Scale Integration (VLSI)VLSI Encyclopedia - Connecting VLSI EngineersVLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.comBlogger478125tag:blogger.com,1999:blog-4978237314452270227.post-87801547859990548212021-06-15T10:42:00.002-07:002021-06-15T10:47:48.037-07:00Top 5 books to refer for a VHDL beginner<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgY7JigOTWFvO_1xnz2ZG4Qj49Z9iGKwAn8I4Yq4M2z1Xj8ZUqO3gdCeFX2IupkayIrXemfdbvk1fUz0xmRZKQrPTxWZpQcmPiOZUIjglI8_bYDOPt15JvN0b79efGV8VAqOpjwlAKuKcBo/s754/BEST_5_VHDL_BOOKS_FOR_BEGINERS.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="502" data-original-width="754" height="426" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgY7JigOTWFvO_1xnz2ZG4Qj49Z9iGKwAn8I4Yq4M2z1Xj8ZUqO3gdCeFX2IupkayIrXemfdbvk1fUz0xmRZKQrPTxWZpQcmPiOZUIjglI8_bYDOPt15JvN0b79efGV8VAqOpjwlAKuKcBo/w640-h426/BEST_5_VHDL_BOOKS_FOR_BEGINERS.jpg" width="640" /></a></div><br /><div style="text-align: justify;"><br /></div><div style="text-align: justify;">VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and application-specific integrated circuits. To start with learning VHDL we are posting here the list of 5 VHDL books which are a good references to get started with VHDL coding.</div><h3 style="text-align: left;"><b>
1. <a href="https://amzn.to/35mRi73" rel="nofollow" target="_blank">VHDL: PROGRAMMING BY EXAMPLE</a> - by Douglas L. Perry</b></h3><div><br /></div><div><a href="https://www.amazon.in/gp/product/0070499446/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=0070499446&linkCode=as2&tag=vlsiencyclope-21&linkId=bf9c0820e841ce70053fe14538703c32" target="_blank"><img border="0" src="//ws-in.amazon-adsystem.com/widgets/q?_encoding=UTF8&MarketPlace=IN&ASIN=0070499446&ServiceVersion=20070822&ID=AsinImage&WS=1&Format=_SL250_&tag=vlsiencyclope-21" /></a> </div><div><br /></div><h3 style="text-align: left;">
2. <a href="https://www.amazon.in/gp/product/0131217887/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=0131217887&linkCode=as2&tag=vlsiencyclope-21&linkId=f129d107d463b7ea7eb07fdd228fbb27" rel="nofollow" target="_blank">Digital Design | With an Introduction to the Verilog HDL, VHDL, and SystemVerilog</a> - by M. Morris Mano</h3><div><br /></div><div>
<a href="https://www.amazon.in/gp/product/0131217887/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=0131217887&linkCode=as2&tag=vlsiencyclope-21&linkId=f129d107d463b7ea7eb07fdd228fbb27" target="_blank"><img border="0" src="//ws-in.amazon-adsystem.com/widgets/q?_encoding=UTF8&MarketPlace=IN&ASIN=0131217887&ServiceVersion=20070822&ID=AsinImage&WS=1&Format=_SL250_&tag=vlsiencyclope-21" /></a> </div><div><br /></div><h3 style="text-align: left;">
3. <a href="https://www.amazon.in/gp/product/9332557160/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=9332557160&linkCode=as2&tag=vlsiencyclope-21&linkId=e14ba0a05ac0fb46885d6b3f7074af07" rel="nofollow" target="_blank">A Vhdl Primer</a> - by Bhasker</h3><div><br /></div><h3 style="text-align: left;">
<a href="https://www.amazon.in/gp/product/9332557160/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=9332557160&linkCode=as2&tag=vlsiencyclope-21&linkId=e14ba0a05ac0fb46885d6b3f7074af07" target="_blank"><img border="0" src="//ws-in.amazon-adsystem.com/widgets/q?_encoding=UTF8&MarketPlace=IN&ASIN=9332557160&ServiceVersion=20070822&ID=AsinImage&WS=1&Format=_SL250_&tag=vlsiencyclope-21" /></a> </h3><h3 style="text-align: left;"> </h3><h3 style="text-align: left;">4. <a href="https://www.amazon.in/gp/product/1259025977/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=1259025977&linkCode=as2&tag=vlsiencyclope-21&linkId=a09ee72be8cb67c62b8fc7ab404f579a" rel="nofollow" target="_blank">Fundamentals of Digital Logic with VHDL Design</a> - by Stephen Brown and Zvonko Vranesic</h3><div><br /></div><div><a href="https://www.amazon.in/gp/product/1259025977/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=1259025977&linkCode=as2&tag=vlsiencyclope-21&linkId=a09ee72be8cb67c62b8fc7ab404f579a" target="_blank"><img border="0" src="//ws-in.amazon-adsystem.com/widgets/q?_encoding=UTF8&MarketPlace=IN&ASIN=1259025977&ServiceVersion=20070822&ID=AsinImage&WS=1&Format=_SL250_&tag=vlsiencyclope-21" /></a> </div><h3 style="text-align: left;"> </h3><h3 style="text-align: left;">5. <a href="https://www.amazon.in/gp/product/8120343018/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=8120343018&linkCode=as2&tag=vlsiencyclope-21&linkId=1b9fbcf393242be81cd152ed3027a994" rel="nofollow" target="_blank">Circuit Design and Simulation With VHDL</a> - by Pedroni V.A</h3><div><br /></div><div><a href="https://www.amazon.in/gp/product/8120343018/ref=as_li_tl?ie=UTF8&camp=3638&creative=24630&creativeASIN=8120343018&linkCode=as2&tag=vlsiencyclope-21&linkId=1b9fbcf393242be81cd152ed3027a994" target="_blank"><img border="0" src="//ws-in.amazon-adsystem.com/widgets/q?_encoding=UTF8&MarketPlace=IN&ASIN=8120343018&ServiceVersion=20070822&ID=AsinImage&WS=1&Format=_SL250_&tag=vlsiencyclope-21" /></a></div><div><br /></div><div><br /></div><div>Please feel free to send your suggestions if there is any good book in your list. We will be happy to share here.</div><div><span> </span><br /></div>VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-7585334932730109012021-06-07T00:00:00.026-07:002021-06-07T00:00:00.170-07:00Effective VIM Editor tips, tricks and plugins to improve coding speed in VLSI<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg2p35eYufP_3-FZZYZ91_Dd6rNVE3clTsIs8bMHnXYK64YtxiQe2Wx-lnnva9k4P2Q8-6mJBJNIimRUn6ipdOBNd8g-nFrLRJObNFZ0syH_e8gZCM-D3QBbmuCPyxm4bGflEJRrxll44E3/s1000/EffectiveTipsforBeginnersToLearnCodingEffectivelyInVLSI.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="516" data-original-width="1000" height="330" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg2p35eYufP_3-FZZYZ91_Dd6rNVE3clTsIs8bMHnXYK64YtxiQe2Wx-lnnva9k4P2Q8-6mJBJNIimRUn6ipdOBNd8g-nFrLRJObNFZ0syH_e8gZCM-D3QBbmuCPyxm4bGflEJRrxll44E3/w640-h330/EffectiveTipsforBeginnersToLearnCodingEffectivelyInVLSI.jpg" width="640" /></a></div><p style="text-align: justify;">One of our colleagues always had to struggle with the Verilog / SystemVerilog syntax. Whenever he opens a .sv file he needs to set the syntax manually as ":set syntax=verilog". This really kills time, especially when you are working on a project with tight schedules. </p><div style="text-align: justify;">So today we are sharing a bunch of good tricks and different plugins that will help you code efficiently, whether Verilog, System Verilog, UVM or scripting languages like Perl. </div><div style="text-align: justify;"><br /></div><div style="text-align: left;"><div style="text-align: justify;">VIM editor is so powerful that everything can be modified using the keyboard. No need to raise a hand to reach out to the mouse. Thus the efficiency of working improves a lot and also looks more professional.</div></div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">By default, vim invokes .vimrc every time a new file is opened. So we may configure any settings upfront in ~/.vimrc for making life easy while working with files.</div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">We will start with basic keyboard shortcuts which will help us to work faster than the actual way.</div><div style="text-align: justify;"><br /></div><h3 style="text-align: justify;">Opening a fine using GVIM</h3><div><div>To open any file from shell type :</div><div>gvim <filename></div><div><br /></div><div>By default, vim invokes .vimrc every time a new file is opened. So we may configure any settings upfront in ~/.vimrc for making life easy while working with files.</div><div><br /></div><div>if you want to open multiple files in tab pages</div><div>gvim -p <filename1> <filename2> ..</div><div><br /></div><div>if you want to open multiple files in horizontal windows</div><div>gvim -o <filenames></div><div><br /></div><div>if you want to open multiple files in vertical windows</div><div>gvim -O <filenames></div></div><h3 style="text-align: left;">Shortcuts for moving the cursor:</h3><div>h - move left</div><div>j - move down</div><div>k - move up</div><div>l - move right</div><h3 style="text-align: left;">Shortcuts for quick editing:</h3><div><div><b>Letter level</b></div><div>r - quickly replaces the letter under the cursor.</div><div>i - change to insert mode. (ready for typing from before the cursor position) Esc to come out of insert mode.</div><div>I - change to insert mode at the start of a line.</div><div>a - change to append mode. (ready for typing after the cursor position), type ESC to come out of append mode.</div><div>A - change to append mode at the end of the line.</div><div>x - deletes the alphabet under the cursor and starts deleting the forward direction.</div><div>X - exactly like the backspace function.</div><div>o - change to insert mode on the next line.</div><div>O - change to insert mode on the previous line.</div><div>f - find a letter in the forward direction of a line.</div><div>F - find a letter in the backward direction of a line.</div></div><div><br /></div><div><b>Word Level</b></div><div>w - move to the start of one word at a time.</div><div><div> You can put any number upfront to move that many words</div><div> Eg: 5w - From 1st word jumps to the start of 6th word.</div><div><br /></div><div>b - move to the beginning of the word at a time.</div><div>e - move to the end of one word at a time.</div><div>y - yanks (that means you can copy a word till the end of a word, or a line, etc by using commands ye, yw, yy, etc)</div><div>p - paste whatever is yanked after the cursor</div><div>P - paste whatever is yanked before the cursor</div><div>d - deletes (that means you can delete a word till the end of a word, or a line, etc by using commands de, dw, dd, etc)</div><div>D - deletes from the cursor position to the end of the line.</div><div>0 - Go to the start of the Line.</div></div><div><br /></div><div><div><b>Other General commands with keys</b></div><div>u - undo</div><div>gg - Go to the start of the file</div><div>G - Go to the end of the file</div><div>ZZ - write, save and close the file</div><div>H - Head of the file in the visible pane</div><div>M - Middle of the file in the visible pane.</div><div>L - Last of the file in the visible pane.</div><div>v- enter visual mode from the alphabet under the cursor.</div><div>V - enter visual mode from the line under the cursor.</div><div>Advanced commands :</div><div>q - recording (will explain this in detail)</div><div>/ - search a word (eg : /<pattern>)</div><div>n- searches any word in forwarding direction</div><div>N - searches any word in the backward direction</div><div>. - repeats the last done job again.</div><div>? - for searching a word backward (more powerful than / )</div><div><br /></div><div><b>Other General commands with additional keys</b></div><div>ctrl + e - scroll in forward direction</div><div>ctrl + p - scroll in backward direction</div><div>ctrl + r - redo</div><div>ctrl + a - increment the number in the line.</div><div>ctrl + x - decrement the number in the line.</div><div>ctrl + q or ctrl + v, enter visual mode in the column.</div><div>Shift + ~ - Invert the text case under the cursor</div><div><div>Vu - if you want to convert the whole line of text under the cursor to a Lowercase line</div><div>VU - if you want to convert the whole line of text under the cursor to an Uppercase line</div></div><div><br /></div><div>In gvim by typing ":" we enter into command line mode, we have a specific set of commands to use at this level.</div></div><div><h4 style="text-align: left;">How do I switch between panes in a split mode in Vim/GVIM ??</h4><div>In command mode, hit Ctrl-W and then a direction, or just Ctrl-W again to switch between panes.</div><div>:b <number> will open the specified buffer in the current pane.</div><div><i>Example :</i> UNIX > vim test_1 test_2 ; # This command opens two test_1 and test_2 files</div><div>But in vim, we can see only one file(by default the first file test_1) with this approach.</div><div>If want to go to the test_2 file then use :b 2</div><div><br /></div><div>:ls will show your open buffers</div><div>If we opened multiple vim files like above and want to know which are in buffer use this command</div><div>and with the help of :b <number>, we can switch between files</div><div><br /></div><div>If we open many windows in vim/gvim and you want to have equal window size for all split pans</div><div>Esc mode Ctrl+W =</div><div>For more info type:</div><div>:help window-resize</div><div><br /></div><div>you can use <ctrl> + w + w To switch the panes in order.</div><div>A suggested way is to put these codes in your vimrc file</div><div><br /></div><div>map <C-j> <C-W>j</div><div>map <C-k> <C-W>k</div><div>map <C-h> <C-W>h</div><div>map <C-l> <C-W>l</div><div><br /></div></div><div><h4 style="text-align: left;">How to remove blank lines from a file?</h4><div>Here's a handy one-liner to remove blank lines from a file.</div><div> :g/^$/d</div><div>Breaking this down. The "g" will execute a command on lines that match a regular expression.</div><div>The regular expression matches blank lines, and the command is "d" (delete).</div><div>You can also use</div><div> :v/./d</div><div>(v means complementary, so any line that doesn’t have a single character at least will be deleted)</div></div><div><h4 style="text-align: left;">How to implement AUTO-COMPLETION </h4><div>Ctrl+p to insert the previous matching word</div><div>Ctrl+n to insert the next matching word</div><div>Ctrl +x followed by Ctrl+l to complete a whole line from the buffer</div><div>(basically ctrl + x pressing will open a sub-mode from there on we can do a lot of stuff.</div><div>for example ctrl + l in submodel gives you to complete the whole line )</div></div><div><br /></div><div><br /></div><div>More content coming soon ....</div>Vishal Patelhttp://www.blogger.com/profile/02237947640542935023noreply@blogger.com1Bengaluru, Karnataka, India12.9715987 77.5945627-15.338635136178846 42.4383127 41.281832536178847 112.7508127tag:blogger.com,1999:blog-4978237314452270227.post-72395522600986835332021-05-04T05:02:00.001-07:002021-05-04T05:04:15.670-07:00UVM Interview Questions - 6<div dir="ltr" style="text-align: left;" trbidi="on"><h2 style="text-align: left;">Q36: What is the Difference between UVM_ALL_ON and UVM_DEFAULT?</h2>
<b>UVM_ALL_ON</b> and <b>UVM_DEFAULT</b> are identical. As per the UVM reference manual:<br />
<br /><b>
UVM_ALL_ON:</b> Set all operations on (default).<br /><b>
UVM_DEFAULT:</b> Use the default flag settings.<br />
<br /><div style="text-align: justify;">It is recommended to use UVM_DEFAULT instead of UVM_ALL_ON even though they both essentially do the same thing today. At some point in time, the class library may add another "bit-flag" which may not necessarily be the DEFAULT.</div><div style="text-align: justify;">If you use UVM_ALL_ON, that would imply that whatever flag it is would be "ON".</div></div><div dir="ltr" style="text-align: left;" trbidi="on"><br /></div><div dir="ltr" style="text-align: left;" trbidi="on"><br /></div><div dir="ltr" style="text-align: left;" trbidi="on"><h3>Q37: What drain time in UVM?</h3><div style="text-align: justify;">The <b>drain time</b> means the access time that you use before ending the simulation. Suppose if we are done with input traffic to the DUT didn't mean that nothing else would happen from that point as the DUT may have required some additional time to complete any transactions that were still being processed. Setting a drain time adds an extra delay from the time that all objections were dropped to the stop of the simulation, making sure that there were no outstanding transactions inside DUT at that point.</div><div><br /></div><div>You can set the drain time in the base test at the end_of_elobration phase as shown below:</div><div><br /></div><div><pre style="background-color: #f8f8f8; border-radius: 2px; border: 1px solid rgb(204, 204, 204); color: #666666; font-family: Consolas, "DejaVu Sans Mono", "Bitstream Vera Sans Mono", monospace; font-size: 13px; letter-spacing: 0.015em; line-height: 15.6px; padding: 0.5em;"><span class="k" style="color: green; font-weight: bold;">class</span> <span class="n">test_base</span> <span class="k" style="color: green; font-weight: bold;">extends</span> <span class="n">uvm_test</span><span class="p">;</span>
<span class="c1" style="color: #408080; font-style: italic;">// ...</span>
<span class="k" style="color: green; font-weight: bold;">function</span> <span class="k" style="color: green; font-weight: bold;">void</span> <span class="n">end_of_elaboration_phase</span><span class="p">(</span><span class="n">uvm_phase</span> <span class="n">phase</span><span class="p">);</span>
<span class="n">uvm_phase</span> <span class="n">main_phase</span> <span class="o">=</span> <span class="n">phase</span><span class="p">.</span><span class="n">find_by_name</span><span class="p">(</span><span class="s" style="color: #ba2121;">"main"</span><span class="p">,</span> <span class="mh">0</span><span class="p">);</span>
<span class="n">main_phase</span><span class="p">.</span><span class="n">phase_done</span><span class="p">.</span><span class="n">set_drain_time</span><span class="p">(</span><span class="k" style="color: green; font-weight: bold;">this</span><span class="p">,</span> <span class="mh">10</span><span class="p">);</span>
<span class="k" style="color: green; font-weight: bold;">endfunction</span>
<span class="c1" style="color: #408080; font-style: italic;">// ...</span>
<span class="k" style="color: green; font-weight: bold;">endclass</span></pre></div><div><br /></div><div><h3>Q38: What is Virtual interface and how Virtual interface is used?</h3></div><div><div style="text-align: justify;"><b>"Virtual interfaces</b> are class data member handles that point to an interface instance. This allows a dynamic class object to communicate with a Design Under Test (DUT) module instance without using hierarchical references to directly access the DUT module ports or internal signals."</div></div><div><br /></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsGJ2pV-dsxSGkyryvHFTNNK9S4R4oul_HOVZKq_AfCF1QIKJKciIn5cnx2HQWYm0KD0Sn5P5NTykUzIxsVWwx53oYepICVTH85QLU0cRUktbSe7nEHHqxLbl6pRAiWUM56pyWwU4qMrZE/s629/Virtual_interface_uvm.png" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="268" data-original-width="629" height="272" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsGJ2pV-dsxSGkyryvHFTNNK9S4R4oul_HOVZKq_AfCF1QIKJKciIn5cnx2HQWYm0KD0Sn5P5NTykUzIxsVWwx53oYepICVTH85QLU0cRUktbSe7nEHHqxLbl6pRAiWUM56pyWwU4qMrZE/w640-h272/Virtual_interface_uvm.png" width="640" /></a></div><br /><div><br /></div><div>Below shown sample code is the easier way to use the virtual interface handles in the UVM environment. </div><div><pre style="background-color: #f8f8f8; border-radius: 2px; border: 1px solid rgb(204, 204, 204); color: #666666; font-family: Consolas, "DejaVu Sans Mono", "Bitstream Vera Sans Mono", monospace; font-size: 13px; letter-spacing: 0.015em; line-height: 15.6px; padding: 0.5em;"><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;">module top;</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> …</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> dut_if dif;</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> …</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> initial begin</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"><br /></div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> uvm_config_db#(virtual dut_if)::set(null, "*", "vif", dif);</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"><br /></div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> run_test();</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"><br /></div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> end</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;">endmodule</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"><br /></div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;">class tb_driver extends uvm_driver #(trans1);</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> …</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> virtual dut_if vif;</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> …</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> function void build_phase(uvm_phase phase);</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> super.build_phase(phase);</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"><br /></div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> // Get the virtual interface handle that was stored in the</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> // uvm_config_db and assign it to the local vif field.</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> if (!uvm_config_db#(virtual dut_if)::get(this, "", "vif", vif))</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> `uvm_fatal("NOVIF", {"virtual interface must be set for: ",</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"><br /></div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> get_full_name(), ".vif"});</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> endfunction</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;"> …</div><div style="color: black; font-family: "Times New Roman"; font-size: medium; letter-spacing: normal; white-space: normal;">endclass </div></pre></div><div style="text-align: justify;">As shown first the actual interface or physical interface handle, <b>dif</b>, is stored into the <b>uvm_config_db</b> at string location "<b>vif</b>" using the <b>set()</b> command just before the <b>run_test()</b> call in the top level module.</div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">Then it shows the use of the <b>get()</b> function of the <b>uvm_config_db</b> to retrieve the virtual interface handle from the same "<b>vif</b>" location and assign it to the local vif virtual interface handle in the driver class (the same code will be used inside of the monitor class as well).<span style="white-space: pre;"> </span></div><div style="text-align: justify;"><br /></div><div style="text-align: justify;"><h3><b><span style="font-size: medium;">Q39: How to add a user-defined phase in UVM?</span></b></h3><p>If needed a user can create user-defined phases in the UVM environment. However, this may impact the re-usability of the component. To define a custom phase user need to extend the appropriate base class for phase-type. Following are the available base classes.</p><p><span> class my_phase extends uvm_task_phase;<br /></span> class my_phase extends uvm_topdown_phase;<br /> class my_phase extends uvm_bottomup_phase;</p><p>You can refer to the <a href="https://www.edaplayground.com/x/3dR4" rel="nofollow" target="_blank">UVM PHASE IMPLEMENTATION EXAMPLE</a> for complete user-defined phase understanding.</p><h3><span style="font-size: medium;">Q40: How interface is passed to components in UVM?</span></h3><div><span style="font-size: medium;">The passing of interface is done using the virtual interface to the component is done using set() and get() methods. consider the below example:</span></div><div><span style="font-size: medium;">Consider we have defined 2 interfaces as</span></div><div><span style="font-size: medium;"><br /></span></div><div><span style="font-size: medium;">apb_if intf0(.pclk(clk));</span></div><div><span style="font-size: medium;">apb_if intf1(.pckl(clk));</span></div><div><span style="font-size: medium;"><br /></span></div><div><span style="font-size: medium;"><b>Setting the interface:</b></span></div><div><span style="font-size: medium;"><div>initial begin</div><div> //put in the database the interface used by APB agent agent0</div><div style="text-align: left;"> uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.env.agent0*", "VIRTUAL_INTERFACE", intf0);</div><div><br /></div><div> //put in the database the interface used by APB agent agent1</div><div style="text-align: left;"> uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.env.agent1*", "VIRTUAL_INTERFACE", intf1);</div><div>end</div></span></div><div><span style="font-size: medium;"><br /></span></div><div><span style="font-size: medium;"><br /></span></div><div><span style="font-size: medium;"><b>Getting the interface:</b></span></div><div><span style="font-size: medium;"><div>class cfs_apb_agent extends uvm_component;</div><div> </div><div> //pointer to the interface</div><div> virtual cfs_apb_if vif;</div><div> </div><div> virtual function void build_phase(uvm_phase phase);</div><div> super.build_phase(phase);</div><div> </div><div> if(uvm_config_db::#(virtual apb_if)::get(this, "", "VIRTUAL_INTERFACE", vif) == 0) begin</div><div> `uvm_fatal("ISSUE", "Could not get from the database the virtual interface for the APB agent")</div><div> end</div><div> endfunction</div><div><br /></div><div>endclass</div></span></div><div><span style="font-size: medium;"><br /></span></div><div><span style="font-size: medium;"><br /></span></div><b><span style="font-size: x-large;"><a href="http://www.vlsiencyclopedia.com/2015/11/uvm-interview-questions-5.html"><< PREVIOUS</a> NEXT >></span></b></div></div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-17625828122753621872020-08-10T03:49:00.001-07:002020-08-10T04:40:45.274-07:00Useful Vim plug-in for efficient coding in Perl<p></p><div class="separator" style="clear: both;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhyiF5ZsVDuI6UvzLxzWdBMvMTX-eY2BwoO7TDGM7tMToTxZfPI6j14qUk3R44Xc5d1vnCVbpUamRDjDcbFar5LK1p4droRL7DT8OlQ6kJCq7CJesKcyCdWhRJhU0jqZ9j2yZnGXXyhagav/s530/perl_script.png" imageanchor="1" style="display: block; margin-left: 1em; margin-right: 1em; padding: 1em 0px; text-align: center;"><img border="0" data-original-height="250" data-original-width="530" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhyiF5ZsVDuI6UvzLxzWdBMvMTX-eY2BwoO7TDGM7tMToTxZfPI6j14qUk3R44Xc5d1vnCVbpUamRDjDcbFar5LK1p4droRL7DT8OlQ6kJCq7CJesKcyCdWhRJhU0jqZ9j2yZnGXXyhagav/s0/perl_script.png" /></a></div>Think of a plug-in with which you can do the following while coding a Perl script:<p></p><p></p><ul style="text-align: left;"><li>Auto addition of file header</li><li>Easy addition of function/frame comment</li><li>Quick inclusion of default code snippet</li><li>Performing syntax check</li><li>Reading documentation about a function</li><li>Converting a full code block to comment, and vice versa</li><li>Help to speed up the code writing with consistency in coding.</li></ul><div>One-stop solution for all these things is a <b><i>perl-support vim plug-in</i></b></div><p></p><p>The <a href="http://www.vim.org/scripts/script.php?script_id=556" rel="nofollow" target="_blank">Perl-Support Vim Plugin</a> – Perl-IDE offers the easiest way to do all of the above, saving a lot of time and keystrokes.</p><p>We have already discussed in an earlier article regarding <a href="http://www.vlsiencyclopedia.com/2020/08/use-of-scripting-languages-in-vlsi.html" rel="nofollow">Use of Scripting languages in VLSI</a></p><p>We will be covering the following in this article</p><p>1. How to install perl-support plugin to use it with VIM.</p><p>2. Powerful features of the <b>Perl-support plugin</b>.</p><p><br /></p><h2 style="text-align: left;"><b><span style="font-size: x-large;">Steps to install Perl-Support VIM Plug-in</span></b></h2><h3 style="text-align: left;"><br /></h3><h3 style="text-align: left;">1. Download the plugin from the vim.org website.</h3><p><a href="http://www.vim.org/scripts/script.php?script_id=556" rel="nofollow" target="_blank">Click here to download to go to the download page</a></p><p>Alternatively use below command</p><pre style="background-color: #eeeeee; border: 1px solid rgb(221, 221, 221); clear: both; color: #111111; font-family: Consolas, Monaco, Menlo, Courier, Verdana, sans-serif; margin-bottom: 26px; margin-top: 0px; overflow-wrap: normal; overflow: auto; padding: 13px; tab-size: 4; text-align: left;"><b><i>cd /usr/src/
wget http://www.vim.org/scripts/download_script.php?src_id=9701</i></b><span style="font-size: 13px;">
</span></pre><h3 style="text-align: left;">2. Copy the zip archive perl-support.zip to $HOME/.vim and run below command</h3><pre style="background-color: #eeeeee; border: 1px solid rgb(221, 221, 221); clear: both; color: #111111; font-family: Consolas, Monaco, Menlo, Courier, Verdana, sans-serif; margin-bottom: 26px; margin-top: 0px; overflow-wrap: normal; overflow: auto; padding: 13px; tab-size: 4;"><i style="color: black; font-family: "Times New Roman"; white-space: normal;"><b> unzip perl-support.zip</b></i></pre><p>This command will create following files:</p><p> $HOME/.vim/autoload/mmtemplates/...</p><p> $HOME/.vim/doc/...</p><p> $HOME/.vim/plugin/perl-support.vim</p><h3 style="text-align: left;">3. Loading of plug-in files must be enabled in $HOME/.vimrc. If not use previously</h3><pre style="background-color: #eeeeee; border: 1px solid rgb(221, 221, 221); clear: both; color: #111111; font-family: Consolas, Monaco, Menlo, Courier, Verdana, sans-serif; margin-bottom: 26px; margin-top: 0px; overflow-wrap: normal; overflow: auto; padding: 13px; tab-size: 4;"><i style="color: black; font-family: "Times New Roman"; white-space: normal;"><b> filetype plugin on</b></i></pre><p>Create <i><b>.vimrc</b></i> if there is none or use the files in $HOME/.vim/perl-support/rc as a starting point.</p><p><br /></p><p>After done with installation lets get to know about</p><h2 style="text-align: left;"><b>The Powerful Features of Perl-support</b></h2><div><b><br /></b></div><h3 style="text-align: left;"><b>1. Add Automatic Header to *.pl file whenever you create a new file</b></h3><h3 style="text-align: left;">2. Insert statements</h3><h3 style="text-align: left;">3. Insert frequently used statements</h3><h3 style="text-align: left;">4. Insert special variables</h3><h3 style="text-align: left;">5. insert code snippets and manage templates</h3><h3 style="text-align: left;">6. Run a profiler</h3><h3 style="text-align: left;">7. Run the script, check the syntax, start the debugger</h3><h3 style="text-align: left;">8. Make integration</h3><div><br /></div><div>Details of all these can be found at </div><div><a href="https://wolfgangmehner.github.io/vim-plugins/perlsupport.html">https://wolfgangmehner.github.io/vim-plugins/perlsupport.html</a></div><div><br /></div><div><br /></div><div><br /></div>VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-16707534319644957232020-08-06T02:57:00.002-07:002020-08-10T23:08:07.893-07:00Use of Scripting languages in VLSI<div class="separator" style="clear: both;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEie9hQOrq2KrKSlwMylNnpcpE9Adc7FVZKOHIuvmgrmSXo3Ds_igBNPvbmaRKuPWMb6lk2F8nfMa91xmF3E7XbMELbMq7GJjnDUqONuRViA083lo_SGZ3_-cvqBRovWQT8PnUiJCbvmwLc/s2721/perl-python-tcl-shell.png" style="display: block; padding: 1em 0px;"><img border="0" data-original-height="1417" data-original-width="2721" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEie9hQOrq2KrKSlwMylNnpcpE9Adc7FVZKOHIuvmgrmSXo3Ds_igBNPvbmaRKuPWMb6lk2F8nfMa91xmF3E7XbMELbMq7GJjnDUqONuRViA083lo_SGZ3_-cvqBRovWQT8PnUiJCbvmwLc/s640/perl-python-tcl-shell.png" width="640" /></a></div><div><br /></div><div>Very often we come across questions from VLSI engineers that "Which scripting language should a VLSI engineer should learn?".</div><div><br /></div><div>Well, Shell, Tcl, Perl, and Python are the scripting languages that are commonly used for VLSI front end/back end design automation and related applications. </div><div><br /></div><div><b>TCL:</b> Tcl (pronounced "tickle" or as an initialism) is a high-level, general-purpose, interpreted, dynamic programming language</div><div><br /></div><div><b>PERL:</b> Practical Extraction and Reporting Language</div><div><br /></div><div><b>PYTHON:</b> Python is a dynamic, object-oriented, high-level programming language that can be used for many kinds of software development/scripting.</div><div><br /></div><div><b>Shell Scripting: </b>A shell script is a computer program designed to be run by the Unix/Linux shell which could be one of the following:</div><div><br /></div><div>The Bourne Shell / The C Shell / The Korn Shell / The GNU Bourne-Again Shell</div><div><br /></div><div>A shell is a command-line interpreter and typical operations performed by shell scripts include file manipulation, program execution, and printing text.</div><div> </div><div>Perl has been in use for several years, but python is increasingly becoming more popular. In the past, we have already shared out views on the advantages of Python. Ref: <a href="http://www.vlsiencyclopedia.com/2016/11/advantages-of-Python-over-Perl.html" rel="nofollow" target="_blank">Advantages of Python over Perl</a></div><div><br /></div><div>Tcl is also used mostly for tool interfaces as several EDA tools support that.</div><div><br /></div><div>If you know any kind of programming, learning a new scripting language will be easy.</div><div><br /></div><div>Following are some commonly used applications of scripting languages in VLSI:</div><div><ul style="text-align: left;"><li>Front end RTL/Testbench code compilation and simulation flows</li><li>Automation of running tests in regressions, generating reports, analyzing failures, debug automation</li><li>Connectivity checks, netlist parsing, automatic generation/modification any RTL module/stubs, etc</li><li>Synthesis, P&R tools interfacing, and back end flow.</li><li>Several project management utilities - regression pass rates, trends, bug charts, etc - that helps in tracking projects</li><li>Any other task that is repetitive in workflow and can be automated.</li></ul><div>Here is a complete comparison of TCL, PYTHON and PERL.</div></div><div><br /></div><div><a href="https://wiki.tcl-lang.org/page/Tcl+vs+Perl+vs+Python" target="_blank">TCL vs PERL vs PYTHON</a></div>Vishal Patelhttp://www.blogger.com/profile/02237947640542935023noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-62325248819849328702020-08-03T07:10:00.000-07:002020-08-03T07:10:15.648-07:00UPF - Unified Power Format<div dir="ltr" style="text-align: left;" trbidi="on">
This is in continuation of our previous post on <a href="http://www.vlsiencyclopedia.com/2019/06/low-power-design-techniques.html">Low Power Design Techniques</a>, where we learned about different types of strategies used to reduce the power consumption in integrated circuits. Here we will discuss about UPF (Unified Power Format). We will learn the following related to UPF.<br />
<br />
What is UPF?<br />When does it started?<br />
How to use UPF in design?<br />
Who supports it?<br />
<br />The below flow shows the stages of design flow and where UPF is used.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh26voCcQBNLCIIZmuaX0cVnj7To2IbURUpFrqCtDUW2KOFye7zQ7jB2EngeQA5423-tQHW4VAjJVovSkbOeKauou9AZDtMZnnvs3YF4EZqQtvX_zYpyE1wq4NXe0QDiKVYBwkMlwqsmZk/s1600/UPF_flow.png" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="1064" data-original-width="808" height="640" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh26voCcQBNLCIIZmuaX0cVnj7To2IbURUpFrqCtDUW2KOFye7zQ7jB2EngeQA5423-tQHW4VAjJVovSkbOeKauou9AZDtMZnnvs3YF4EZqQtvX_zYpyE1wq4NXe0QDiKVYBwkMlwqsmZk/s640/UPF_flow.png" width="483" /></a></div>
<div class="separator" style="clear: both; text-align: left;">
<br /></div>
<div class="separator" style="clear: both; text-align: left;">
<b>What is UPF?</b></div>
<div class="separator" style="clear: both; text-align: left;">
The Unified Power Format (UPF). It is intended to ease the job of specifying, simulating, and verifying IC designs that have a number of power states and power islands.</div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;">Unified Power Format (UPF) is an industry-wide power format specification to implement low power techniques in a power-aware design flow. UPF is designed to reflect the power intent of a design at a relatively high level. UPF scripts help describe power intent such as:</div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;">* Which power rails to be routed to individual blocks.</div><div class="separator" style="clear: both; text-align: left;">* When blocks are expected to be powered up or shut down. </div><div class="separator" style="clear: both; text-align: left;">* How voltage levels should be shifted between two different power domains. </div><div class="separator" style="clear: both; text-align: left;">* And type of measures taken for memory cells and retention registers contents if the primary power supply to a domain is removed. </div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;">Hence making the design to be more power-efficient. With power becoming an important factor in today's electronic systems, there is a need for a more systematic approach to reduce the power in complex designs; and UPF is developed to address this need.</div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;"><b>When does it started?</b></div><div class="separator" style="clear: both; text-align: left;">A Unified Power Format (UPF) technical committee was formed by the Accellera organization, chaired by Stephen Bailey of Mentor Graphics. As a reaction to the Power Forward Initiative, the group was proposed in July 2006 and met on September 13, 2006.[1] It submitted its first draft in January 2007, and a version 1.0 was approved to be published on February 26, 2007. Joe Daniels was a technical editor.</div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;"><b>How to use UPF in design?</b></div><div class="separator" style="clear: both; text-align: left;"><div class="separator" style="clear: both;">Tcl, the tool control language is the backbone of UPF, as well as the similar Common Power Format (CPF), Tcl is a scripting language originally created to provide a way to automate the control of design software.</div><div class="separator" style="clear: both;"><br /></div><div class="separator" style="clear: both;">The attraction of Tcl is that command-line commands can be used as statements in a script. Most Tcl implementations are specific to an individual tool. However, the CPF and UPF definitions are unusual in that they are meant to be used with all tools in a power-aware flow – the tools themselves have to determine whether the commands supplied in the Tcl script are relevant to them or not.</div><div class="separator" style="clear: both;"><br /></div><div class="separator" style="clear: both;">The Tcl command “create_power_domain”, for example, is used by UPF-aware tools to define a set of blocks in the design that are treated as one power domain that is supplied differently to other blocks on the same chip. The idea behind this type of command is that power-aware tools read in the description of which blocks in a design can be powered up and down independently. The tools can use that information to determine, for example, how the simulation will behave under different conditions.</div><div class="separator" style="clear: both;"><br /></div><div class="separator" style="clear: both;">For example, a testbench written in SystemVerilog may identify to the simulator that a particular block should be powered down to ensure that other blocks do not access it without checking on power status first.</div><div class="separator" style="clear: both;"><br /></div><div class="separator" style="clear: both;">A transistor-level simulation may use the power definitions to see what happens when supply voltages or substrate bias voltages change. Do all the necessary logic paths meet expected timing when the supply voltage to one block is lowered to save power while others are running at their maximum voltage? Similarly, a static analysis tool may check that the correct level shifters are in place to determine whether blocks in different power domains can communicate.</div></div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;"><b>Who support it?</b></div><div class="separator" style="clear: both; text-align: left;">A number of EDA vendors have chosen to support UPF in their flows, including Mentor Graphics and Synopsys. However, support is not universal. Cadence Design Systems supports the Common Power Format originally developed by the company but which is now administered by the Silicon Integration Initiative but has declared support for the latest version of IEEE 1801, which incorporates a number of features from CPF.</div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;">Let us know in the comments if you wish to know about any specific details regarding UPF.</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-43290853209381839172020-04-02T02:03:00.000-07:002020-04-02T02:03:58.587-07:00Understanding Logic gates at transistor level : Not Gate<div dir="ltr" style="text-align: left;" trbidi="on">
<div>
<div style="text-align: justify;">
Today we will talk about some basics of digital logic gates. It's about using the transistor for the construction of logic gates. Transistors are used in the construction of logic gates as they act as fast switches. </div>
<div style="text-align: justify;">
When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to the emitter may be near zero and can be used to construct gates for the TTL logic family. Let's start with simple NOT gate.</div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
1. Not Gate using transistor</div>
<div style="text-align: justify;">
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEizUyJvEturIgsZeHo1BGx1a3Erv7vgT3oQhu1FC0Hj31Nnw42rrHxf4O7Srsm-qPDjU0PvcJH68oiFBZRcCVyUCAGkH6W1rWjYk15Ef62EXZrDKlAcnmkaet4khLWa79toWzHgI3S8C23l/s1600/Introduction-to-NOT-Gate-1024x469%257E2.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="395" data-original-width="1024" height="123" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEizUyJvEturIgsZeHo1BGx1a3Erv7vgT3oQhu1FC0Hj31Nnw42rrHxf4O7Srsm-qPDjU0PvcJH68oiFBZRcCVyUCAGkH6W1rWjYk15Ef62EXZrDKlAcnmkaet4khLWa79toWzHgI3S8C23l/s320/Introduction-to-NOT-Gate-1024x469%257E2.png" width="320" /></a></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhPl6KlVQnDlQOq2HpRZMuy0Qxf33fgs2xLsEDosKpF6N9eER5bHi-PyPe_jtoiJUiYcLsu_S_jaIBWEU2NBdzxQgOXj1VsRm73gSEQ09B91AQI8_7vQ3o3kCh-tjndmLGS0ottfhD_CycW/s1600/electronic-circuit-of-not-gate.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="273" data-original-width="279" height="195" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhPl6KlVQnDlQOq2HpRZMuy0Qxf33fgs2xLsEDosKpF6N9eER5bHi-PyPe_jtoiJUiYcLsu_S_jaIBWEU2NBdzxQgOXj1VsRm73gSEQ09B91AQI8_7vQ3o3kCh-tjndmLGS0ottfhD_CycW/s200/electronic-circuit-of-not-gate.jpg" width="200" /></a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
</div>
<div style="text-align: justify;">
NOT gates are single-input devices which have an output level that is normally at logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level “1”, in other words, it “inverts” (complements) its input signal. The output from a NOT gate only returns “HIGH” again when its input is at logic level “0” giving us the Boolean expression <span class="otxt">A</span> = Q.<br />
<br />
The input of the NOT Gate is connected at the base of the transistor and the output is taken from the collector. The transistor here acts as the switch so when the voltage is applied at the base of the transistor the transistor starts conducting and shorts the output to the ground similarly when no voltage is applied at the input the output is connected to the Vcc as shown thus in this way the circuit implements the NOT function.</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-28488966569054374472019-06-24T23:26:00.001-07:002021-06-16T09:50:19.830-07:00Low Power Design Techniques<div dir="ltr" style="text-align: left;" trbidi="on">
<div dir="ltr">
In today's IOT (Internet Of Things) world there are various wearable/Portable smart devices coming up in the market which are battery operated. These devices also need to be Power efficient such that it can run on battery for a long time. And here the concept of Low Power Design comes into existence.</div>
<div dir="ltr">
<br />
Different types of strategies used to reduce power consumption. Some of them are listed below.<br />
<br />
<b>1. Clock Gating</b><br />
Clock being the highest frequency toggling signal contributes maximum towards the dynamic power consumption in the SoC even when the flops that are being fed by the clock are not changing their state. So, it is practical to gate the clock from reaching the set of registers or maybe some block in the design. This will ensure that there is no switching activity due to change in the clock and hence reduction in dynamic power consumption.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjo3UVogv66rf6MKdRdeII2ZDIbLDPMG8WhrxL3UQJE6db4qlg1nW5wmLlGZax_wtxFlfGNoJG6RKg-XTNLflsrdCelaCzHJWRwrg8y1Z54GpuiQq4I3w9luSlFPf168hl8Q1YqYXsekS7I/s1600/latch_based_clock_gating.jpeg" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="147" data-original-width="387" height="151" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjo3UVogv66rf6MKdRdeII2ZDIbLDPMG8WhrxL3UQJE6db4qlg1nW5wmLlGZax_wtxFlfGNoJG6RKg-XTNLflsrdCelaCzHJWRwrg8y1Z54GpuiQq4I3w9luSlFPf168hl8Q1YqYXsekS7I/s400/latch_based_clock_gating.jpeg" width="400" /></a></div>
<br />
<b>2. Power gating</b><br />
Power gating is a technique to shut down the power of a block when it is not required to be On. i.e In Mobile voice processing block can be shut down when the user is not having an incoming or outgoing call. This is the best method of reducing power consumption.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiW93pdPlkl8EhA5iHLiL3_eeBYlHhHd-4L9ysAHIem4G5UPhrLeDBUI1JVbysh5ZQudS8wm2G2W7y8Wi952DixISoADwqt57v7LBjuaIS2MEnZvT0-hYyR4-NOu4TgpbdzSHx6y-3Jh4uR/s1600/pwer_gating.png" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="554" data-original-width="382" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiW93pdPlkl8EhA5iHLiL3_eeBYlHhHd-4L9ysAHIem4G5UPhrLeDBUI1JVbysh5ZQudS8wm2G2W7y8Wi952DixISoADwqt57v7LBjuaIS2MEnZvT0-hYyR4-NOu4TgpbdzSHx6y-3Jh4uR/s320/pwer_gating.png" width="220" /></a></div>
<br />
<br />
<br />
<b>3. Multiple Vt Library cells</b><br />
Nowadays the user provides the same cells with two different threshold voltage in the library. So that synthesis tools can choose cells depending on the requirement. With low Vt, sub-threshold leakage will increase but speed will also be higher. So for timing critical path synthesis tool will insert low Vt cells and at another path high Vt cell.<br />
<br />
<b>4. Dynamic voltage and frequency scaling</b><br />
Dynamic Voltage and Frequency Scaling (DVFS) describes the use of two power saving techniques (dynamic frequency scaling and dynamic voltage scaling). In this technique same block can be working at the different voltage at the different time .i.e some time it is required to do high computation (complex equation solver) task then it needs more speed so it can operate at high voltage. While some time low computation is required so it can operate at a lower voltage.<br />
<br />
<b>5. Supply voltage reduction</b><br />
As power is directly proportional to voltage (p =iv), with a reduction in voltage, power consumption will reduce. But again with a reduction in voltage will reduce switching speed as well.<br />
<br />
<b>6. Multi-voltage design</b><br />
In SOC some block ( RAM) are such which require higher speed, so that block can be powered with higher voltage. While some block (Peripheral device) which does not needs high speed so that block can be powered with lower voltage, which in turn can reduce leakage power. In earlier days people used to have the same voltage for the whole design which makes it necessary to operate at high voltage. While this new technique, we can achieve leakage reduction.<br />
<br />
In upcoming posts, we will discuss more on <a href="https://www.vlsiencyclopedia.com/2020/07/upf-unified-power-format.html" target="_blank">UPF(Unified Power Format)</a> and low power verification.</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-47565534631548263962017-03-26T21:17:00.000-07:002017-03-26T21:52:09.340-07:00Understanding real, realtime and shortreal variables of SystemVerilog<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
This post will help you to understand the difference between<b> real, realtime and shortreal</b> data types of SystemVerilog and its usage.</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div>
<div style="text-align: justify;">
We faced some issue with real and realtime variable while writing a timing check.</div>
<div style="text-align: justify;">
Below is a simplified example of that check. </div>
<br />
<span style="font-family: "courier new" , "courier" , monospace;">`timescale 1ns/1fs;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;">module test; </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> real a,b; </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> realtime t1, t2;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">initial </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">begin </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t1 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1.8ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t2 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> b = 1.8;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> a = t2 - t1; </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;"> if(a == b)</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("PASS a = %f b = %f", a,b);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> else</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("FAIL a = %f b = %f", a,b);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">end </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">endmodule </span><br />
<br />
and here is what we got the display<br />
<br />
<span style="font-family: "courier new" , "courier" , monospace;">FAIL a = 1.800000 b = 1.800000 </span><br />
<br />
How that happened !!! is really <i>1.800000 != 1.800000 !!!!</i><br />
<br />
Now let's try something else, instead of using <b>real</b> we use <b>shortreal</b><br />
<br />
<span style="font-family: "courier new" , "courier" , monospace;">`timescale 1ns/1fs;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;">module test; </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> shortreal a,b; </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> realtime t1, t2;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">initial </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">begin </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t1 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1.8ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t2 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> b = 1.8;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> a = t2 - t1; </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;"> if(a == b)</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("PASS a = %f b = %f", a,b);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> else</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("FAIL a = %f b = %f", a,b);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">end </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">endmodule </span><br />
<br />
Now the result was as expected !!<br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">PASS a = 1.800000 b = 1.800000 </span><br />
<br />
<div style="text-align: justify;">
To understand this lets go to <a href="http://www.vlsiencyclopedia.com/2012/06/systemverilog-language-reference-manual.html" target="">SystemVerilog LRM</a>. As per LRM </div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div>
<div style="text-align: justify;">
The real data type is from Verilog-2001, and is the same as a <b>C double</b>. </div>
</div>
<div>
<div style="text-align: justify;">
The shortreal data type is a SystemVerilog data type, and is the same as a <b>C float</b>.</div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
So float is 32 bit data type and double is 64 bit data type. This sounds cool but still how 1.800000 != 1.800000</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
No ! it's not only about being 32 or 64 bit data type its more about precision.<i>"</i><i><b>Precision</b> is the main difference where <b>float</b> is a single precision (<b>32 bit</b>) floating point data type, <b>double</b> is a double precision (<b>64 bit</b>) floating point data type "</i>.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
To understand this difference let's go beyond and print the values with more number of digits after decimal point.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
In below example we have used both real and shortreal to see the difference.</div>
<br />
<span style="font-family: "courier new" , "courier" , monospace;">`timescale 1ns/1fs;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;">module test; </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> real a,b;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> shortreal c,d;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> realtime t1, t2, t3, t4;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">initial </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> begin </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t1 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1.8ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t2 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> b = 1.8;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> a = t2-t1;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;"> if(a == b)</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("Case1: PASS \na = %1.100f \nb = %1.100f", a,b);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> else</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("Case1: FAIL \na = %1.100f \nb = %1.100f", a,b);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> end </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">initial </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> begin </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t3 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> #1.8ns;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> t4 = $realtime;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> d = 1.8;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;"> c = t2-t1;</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;"> if(c == d)</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("Case2: PASS \nc = %1.100f \nd = %1.100f", c,d);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> else</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> $display("Case2: FAIL \nc = %1.100f \nd = %1.100f", c,d);</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"> end </span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">endmodule</span><br />
<br />
Here is what the display is<br />
<br />
<span style="font-family: "courier new" , "courier" , monospace;">Case1: FAIL </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">a = 1.7999999999999998223643160599749535322189331054687500000000000000000000000000000000000000000000000000 </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">b = 1.8000000000000000444089209850062616169452667236328125000000000000000000000000000000000000000000000000</span><br />
<span style="font-family: "courier new" , "courier" , monospace;"><br /></span>
<span style="font-family: "courier new" , "courier" , monospace;">Case2: PASS </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">c = 1.7999999523162841796875000000000000000000000000000000000000000000000000000000000000000000000000000000 </span><br />
<span style="font-family: "courier new" , "courier" , monospace;">d = 1.7999999523162841796875000000000000000000000000000000000000000000000000000000000000000000000000000000</span><br />
<br />
<div style="text-align: justify;">
It's clearly seen that the <b>64 bit real variable has more precision that that or 32 bit shortreal variable</b>. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Here one more thing to consider is that we are taking difference of time. <b><i>Floating point math is not exact</i>.</b> Simple values like 0.1 cannot be precisely represented using binary floating point numbers, and the limited precision of floating point numbers means that slight changes in the order of operations or the precision of intermediates can change the result. That means that comparing two floats to see if they are equal is usually not what you want.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The things will not matter much if you are doing calculations in <b>nanoseconds </b>so we suggest to use <b>shortreal</b> instead of <b>real</b>.</div>
</div>
</div>
</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com1tag:blogger.com,1999:blog-4978237314452270227.post-13514291212119561192017-01-15T08:54:00.000-08:002017-01-15T08:55:15.304-08:002017 VLSI Symposia on VLSI Techology and Circuits<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgK2srjBC_EwtpW7w4spC9Md7OfpS1ulkf27z_Fbn-tUQkFv705xAzs4ECk_v_ir4lmWzNGcWM-Lgh_KoNUOEZQIdNuG1asYG8bhpUS9GRJPFSuU8-1cRvnxVoOiTLmlUGy3auJp3V3rhzO/s1600/VLSI_2017.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="224" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgK2srjBC_EwtpW7w4spC9Md7OfpS1ulkf27z_Fbn-tUQkFv705xAzs4ECk_v_ir4lmWzNGcWM-Lgh_KoNUOEZQIdNuG1asYG8bhpUS9GRJPFSuU8-1cRvnxVoOiTLmlUGy3auJp3V3rhzO/s640/VLSI_2017.jpg" width="640" /></a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
For the past 30 years, the combined annual Symposia on VLSI Technology and Circuits have provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees. A single registration enables participants to attend both Symposia.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Online paper submission:</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Online paper submissions are now open for the 2017 Symposia on <b>VLSI Technology and Circuits, to be held at the Rihga Royal Hotel in Kyoto, Japan from June 5 – 8, 2017</b>. In a departure from previous years, both Symposia (VLSI Technology and VLSI Circuits) will be held on a fully overlapping schedule from June 6 – 8, preceded by Short Courses on June 5.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>The deadline for paper submissions to both Symposia is January 23, 2017</b>. Complete details for paper submission can be found online at: <a href="http://vlsisymposium.org/authors.html">http://vlsisymposium.org/authors.html</a></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
This year’s Symposia theme is “Harmonious Integration Toward Next Dimensions.” Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module level, with co-optimization of device technology and circuit/system design, including focus areas in the Internet of Things (IoT), industrial electronics, ‘big data’ management, artificial intelligence (AI), biomedical applications, virtual reality (VR) / augmented reality (AR), robotics and smart cars. These topics will be featured in focus sessions as part of the program.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<ul>
<li>IoT systems & technologies, including ultra-low power, heterogeneous integration, wearable devices, sensors, connectivity, power management, digital/analog, microcontrollers and application processors</li>
<li>Stand-alone & embedded memories, including technology & reliability for DRAM, SRAM, (3D-)NAND, MRAM, PCRAM, ReRAM and emerging memory technologies</li>
<li>CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization</li>
<li>RF / analog / digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors</li>
<li>Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling</li>
<li>Packaging technologies & System-in-Package (SiP), including through-silicon vias (TSVs), power & thermal management, inter-chip communication, 3D-system integration, as well as yield & test issues</li>
<li>Photonics Technology & ‘Beyond CMOS’ devices</li>
</ul>
<br />
<div style="text-align: justify;">
The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<ul>
<li>Digital circuits, processors and architectures, including circuits and techniques for standalone and embedded processors</li>
<li>Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies</li>
<li>Frequency generation and clock circuits for high-speed digital and mixed-signal applications</li>
<li>Analog and mixed-signal circuits, including amplifiers, filters and data converters</li>
<li>Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications</li>
<li>Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications</li>
<li>Power conversion circuits, including battery management, voltage regulation, and energy harvesting</li>
<li>Imagers, displays, sensors, VLSI circuits & systems for biomedical, healthcare and wearable applications</li>
</ul>
<br />
<div style="text-align: justify;">
Joint Technology & Circuits focus sessions feature invited and contributed papers highlighting innovations and advances in the following areas of joint interest:</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<ul>
<li>IoT /ULP (Internet of Things / Ultra Low Power) devices: Advanced CMOS processes for ULP, design enablement, design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability</li>
<li>New Computing: Artificial intelligence, ‘beyond von Neumann’ computing, machine learning, neuromorphic & in-memory / in-sensor computing</li>
<li>2D MOSFETs / New concepts for channel & gate materials: Graphene, MoS2, α-Si / poly-Si or flexible organic materials for ‘More than Moore’ devices</li>
<li>Emerging memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, and MRAM, Memristor, 3D Xpoint memory technologies</li>
<li>Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes</li>
<li>3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and applications</li>
</ul>
<br />
<div style="text-align: justify;">
<b>Best Student Paper Award</b></div>
<div style="text-align: justify;">
Awards for best student paper at each Symposia are chosen based on the quality of the papers and presentations. The recipients will receive a monetary award, travel cost support and a certificate at the opening session of the 2018 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Sponsoring Organizations</b></div>
<div style="text-align: justify;">
The Symposium on VLSI Technology is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The Symposium on VLSI Circuits is sponsored by the IEEE Solid State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Further Information, Registration and Official Call for Papers</b></div>
<div style="text-align: justify;">
Visit: <a href="http://www.vlsisymposium.org/">http://www.vlsisymposium.org</a>.</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-26042786400812532782016-11-21T09:00:00.001-08:002021-06-11T04:07:13.956-07:00Advantages of Python over Perl<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhWy-a3ebSjqMy_1Osp5xmfQdj5ezOnWIoQzz293ggjndLXPAhjNc44qY6yrbZiT__M96z2gXkvA4KnhgLQKa33sHPRr0P8WWST8eUkYCP1mll6_8rMTe95gXBtH88Vy3_fEJPjUG3IEClN/s1600/Python_Perl.jpg" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"><img border="0" height="240" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhWy-a3ebSjqMy_1Osp5xmfQdj5ezOnWIoQzz293ggjndLXPAhjNc44qY6yrbZiT__M96z2gXkvA4KnhgLQKa33sHPRr0P8WWST8eUkYCP1mll6_8rMTe95gXBtH88Vy3_fEJPjUG3IEClN/s320/Python_Perl.jpg" width="320" /></a></div>
<div style="text-align: justify;">
In the new competitive generation of chip designing where Time-to-Market is so critical and also the complexity of designs is increasing exponentially. Adding to that it is also observed that the Verification is always considered the longest pole and takes nearly 70% of the chip design life cycle. Hence any opportunity to automate a task that is repeatable more than once is considered of most importance to improve the verification productivity. This is where “scripting” skills are highly valuable for any Verification engineer.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
After many years of writing design and verification automation scripts in Perl and Python, we would like to throw some light on the advantages of using Python.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Maintainability</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
As we all know, Perl is easy to write but hard to read, especially when someone else has written it. There are multiple ways of writing the same code. Add to this fact that many engineers take pride in writing highly obfuscated Perl that is a pain for others to read.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Maintainability is a critical aspect of any engineering project. Throwing away code and rewriting it is a productivity loss. Unfortunately, this happens a lot with Perl.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Python, on the other hand, has a clean syntax and typically there is only one way of doing what you want. Python code is hence much more readable. Even people who have never written Python code ever can understand it, as the syntax is very “pseudo-code” like. It is also easier to functionalize and modularize code in Python as the language naturally encourages this.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Re-usability</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Perl is designed for use and throw. You write something in Perl, run it and then forget about it. It is very difficult to extend the functionality of a Perl script. Typically you would not have organized your code into functions, as Perl syntax does not encourage that. When you try adding some functionality to your Perl script you realize that re-writing it completely is better than re-using the earlier script and extending it.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Python syntax encourages re-usability. The mindset is different. When you write code in Python, you write with future re-usability in mind. This is really tough to do in Perl. Perl encourages shortcuts.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Scale</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Writing large pieces of code (more than 50k lines) in Perl exposes the weaknesses in the language. Maintainability, performance, and packaging are big issues. Can I package my application in a way that doesn’t require users to download and install modules used by the application?</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Perl encourages users to download and install modules as needed. IT departments are not comfortable with upgrading Perl installations on thousands of server farm nodes. It would be an IT nightmare.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Python distributions, on the other hand, come with a majority of the module libraries included. Also, Python allows the packaging of applications so users do not have to manually download and install all module and library dependencies needed to run an application.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Final words</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Perl is great at some things. For example, it has fantastic regular expression capabilities (it can even combine multiple regexp’s and match all of them together!). Perl is a worthy successor to awk.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Bottom line: For use and throw scripts, Perl is great. But, if your code needs to be checked into a version control system and will potentially be modified by other people, I would prefer Python over Perl.</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-89758365551277462792016-11-19T10:55:00.001-08:002016-11-19T10:55:37.558-08:00Transaction Recording In Verilog Or System Verilog<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="MsoNormal" style="margin-bottom: 0.0001pt;">
<div class="MsoNormal">
<o:p></o:p></div>
<span style="font-family: "cambria" , serif;">As there is not
yet a standard for <b>transaction recording</b> in Verilog or VHDL, ModelSim includes
a set of system tasks to perform transaction recording into a WLF file. </span><span style="font-family: "cambria" , "serif"; font-size: 12.0pt;">Transaction modeling allows users to
raise the level of description, analysis and debugging of their designs to the
transaction level. </span><span style="font-family: "cambria" , "serif"; font-size: 12.0pt;">A transaction represents a transfer of
high-level data or control information between the test bench and the design
under test (DUT) over an interface or any sequence of signal transitions
recorded in the simulation database as a transaction.<o:p></o:p></span><br />
<span style="font-family: "cambria" , "serif"; font-size: 12.0pt;"><br /></span>
<br />
<div class="MsoNormal">
<span style="font-family: "cambria" , "serif";">The API is the
same for <b>Verilog</b> and <b>SystemVerilog</b>. As stated previously, the name
"Verilog" refers both to Verilog and SystemVerilog unless otherwise
noted.<o:p></o:p></span></div>
<div class="MsoNormal">
<a href="https://draft.blogger.com/null" name="wp1137937"></a><span style="font-family: "cambria" , "serif";">The
recording APIs for Verilog and VHDL are a bit simpler than the SCV API.
Specifically, in Verilog and VHDL:<o:p></o:p></span></div>
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal"><a href="https://draft.blogger.com/null" name="wp1137938"></a><span style="font-family: "cambria" , "serif";">There is no
database object as there is in SCV; the database is always WLF format (a <i>.wlf</i> file).<o:p></o:p></span></li>
</ul>
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal"><a href="https://draft.blogger.com/null" name="wp1137939"></a><span style="font-family: "cambria" , "serif";">There is no
concept of begin and end attributes All attributes are recorded with the
system task <b>$add_attribute() </b>or add_attribute.<o:p></o:p></span></li>
</ul>
<span style="font-family: "cambria" , "serif"; font-size: 12.0pt;">
</span><br />
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal"><a href="https://draft.blogger.com/null" name="wp1137940"></a><span style="font-family: "cambria" , "serif";">Your design
code must free the transaction handle once the transaction is complete and
all use of the handle for relations or attribute recording is complete.
(In most cases, SystemC designs ignore this step since SCV frees the
handle automatically.)</span></li>
</ul>
</div>
<div class="MsoNormal" style="margin-bottom: 0.0001pt;">
<span style="font-family: "cambria" , "serif"; font-size: 12.0pt;">A transaction has a begin time, an end
time, and attributes. Examples of transactions include read operations, write
operations, and packet transmissions. The transaction level is the level at
which many users think about the design, so it is the level at which you can
verify the design most effectively.<o:p></o:p></span></div>
<div class="MsoNormal" style="margin-bottom: 0.0001pt;">
<br /></div>
<div class="MsoNormal" style="margin-bottom: 0.0001pt;">
</div>
<div class="MsoNormal" style="margin-bottom: 0.0001pt;">
<span style="font-family: "cambria" , "serif"; font-size: 12.0pt;">Transactions are recorded on a stream. A
stream is a collection of transactions, recorded over time. A stream has a
name, and usually exists somewhere within the test bench hierarchy – for
example a driver might have a stream which represents all the transactions that
have occurred on that driver. Each driver defines a collection of attributes (
transaction items ) which are defined by users, and which are meaningful to the
transaction. The values of attributes are set for each transaction. Finally,
transactions can be linked to each other. A link has a direction and a
user-defined name, and specifies a relation between the two transactions.<o:p></o:p></span><br />
<span style="font-family: "cambria" , "serif"; font-size: 12.0pt;"><br /></span>
<br />
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<span style="font-family: "courier new"; font-size: 10pt;">module top;<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138071"></a><span style="font-family: "courier new"; font-size: 10pt;"> integer stream, tr;<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138072"></a><a href="https://draft.blogger.com/null" name="wp1138073"></a><span style="font-family: "courier new"; font-size: 10pt;"> initial begin<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138074"></a><span style="font-family: "courier new"; font-size: 10pt;"> stream =
$create_transaction_stream("Stream");<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138075"></a><span style="font-family: "courier new"; font-size: 10pt;"> #10;<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138076"></a><span style="font-family: "courier new"; font-size: 10pt;"> tr = $begin_transaction(stream,
"Tran1");<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138077"></a><span style="font-family: "courier new"; font-size: 10pt;"> $add_attribute(tr, 10,
"beg");<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138078"></a><span style="font-family: "courier new"; font-size: 10pt;"> $add_attribute(tr, 12,
"special");<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138079"></a><span style="font-family: "courier new"; font-size: 10pt;"> $add_attribute(tr, 14,
"end");<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138080"></a><span style="font-family: "courier new"; font-size: 10pt;"> #4;<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138081"></a><span style="font-family: "courier new"; font-size: 10pt;"> $end_transaction(tr);<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138082"></a><span style="font-family: "courier new"; font-size: 10pt;"> $free_transaction(tr);<o:p></o:p></span></div>
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138083"></a><span style="font-family: "courier new"; font-size: 10pt;"> end<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="background: white; margin: 0in 0in 0.0001pt 27.35pt;">
<a href="https://draft.blogger.com/null" name="wp1138084"></a><a href="https://draft.blogger.com/null" name="wp1138085"></a><span style="font-family: "courier new"; font-size: 10pt;">endmodule<o:p></o:p></span></div>
</div>
<br />
<div>
<span style="font-family: "cambria" , serif;">Here,</span><br />
<span style="font-family: "cambria" , serif;"><br /></span>
<span style="font-family: "cambria" , serif;"><b>1. $</b></span><span style="font-family: "cambria" , serif;"><b>create_transaction_stream()</b>
is used to define a transaction stream. You can use this system task to create
one or more stream objects.</span><br />
<br />
module top;<br />
integer hStream<br />
<br />
initial begin<br />
hStream = $create_transaction_stream("stream", "transaction");<br />
.<br />
.<br />
end<br />
.<br />
.<br />
endmodule<br />
<br />
<div class="MsoNormal">
<span style="font-family: "cambria" , serif;"><b>2. $begin_transaction</b>
is used to start a transaction by providing a valid handle of the transaction
as shown below.<o:p></o:p></span></div>
<div class="MsoNormal">
<br />
<br />
integer hTrans;<br />
.<br />
.<br />
hTrans = $begin_transaction(hstream, "READ");<br />
<div>
<br /></div>
</div>
<div>
</div>
<br />
<div class="MsoNormal">
<span style="font-family: cambria, serif;">In this
example, we begin a transaction named "READ" on the stream already
created. The $begin_transaction system function accepts other parameters to
specify: the start time for the transaction, and any relationship information,
including its designation as a phase transaction.</span></div>
</div>
<div class="MsoNormal">
<span style="font-family: "cambria" , serif;">The return
value is the handle for the transaction. It is needed to end the transaction or
record attribute.</span><o:p></o:p></div>
<div class="MsoNormal">
<span style="font-family: "cambria" , serif;"><br /></span>
<span style="font-family: "cambria" , serif;"><b>3.</b> <b>$end_transaction</b> has a single required argument – the handle of the transaction that is to be ended. It also has a single optional argument, the time in the past that this transaction ended. After a transaction has been ended, the transaction handle can still be used to add attributes and create relations.</span></div>
<div class="MsoNormal">
<span style="font-family: "cambria" , serif;"><br /></span>
<span style="font-family: cambria, serif;">$end_transaction( </span><span style="font-family: cambria, serif;">handle transaction </span><span style="font-family: cambria, serif;">[, time endTime])</span><br />
<span style="font-family: cambria, serif;"><b><br /></b></span>
<span style="font-family: cambria, serif;"><b>4.</b> <b>$free_transaction</b> has a single argument – the handle of the transaction to be deleted. Once a transaction is deleted the handle becomes invalid. It cannot be used in any other recording interfaces.</span><br />
<span style="font-family: cambria, serif;"><br /></span>
<span style="font-family: cambria, serif;">$free_transaction (</span><span style="font-family: cambria, serif;">handle transaction)</span><br />
<span style="font-family: cambria, serif;"><br /></span>
<span style="font-family: cambria, serif;"><b>5. $add_attribute</b> has two required arguments – a transaction handle on which the attribute is to be created and the attribute that is to be recorded. There is one optional argument of type string named attributeName. This attributeName specifies an alias name for the attribute. If not specified, the name used for the attribute is the actual name of the SystemVerilog object.</span><br />
<span style="font-family: cambria, serif;"><br /></span>
<span style="font-family: cambria, serif;">$add_attribute( </span><span style="font-family: cambria, serif;">handle transaction, </span><span style="font-family: cambria, serif;">object attributeValue </span><span style="font-family: cambria, serif;">[, string attributeName])</span><br />
<span style="font-family: cambria, serif;"><br /></span>
<span style="font-family: cambria, serif;"><b>6. $add_relation</b> has three arguments – the first two are the two transaction handles which are related. The third argument is the string name of the relation.</span><br />
<span style="font-family: cambria, serif;"><br /></span>
<span style="font-family: cambria, serif;">$add_relation( </span><span style="font-family: cambria, serif;">handle sourceTransaction, </span><span style="font-family: cambria, serif;">handle targetTransaction, </span><span style="font-family: cambria, serif;">string relationshipName)</span><br />
<div>
<br /></div>
</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-2851218269159288522016-10-22T11:43:00.001-07:002016-10-22T11:47:03.656-07:00Build smart tests using uvm_report_catcher<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhqIlUQER4QlPi9XhfaQjzlCKeQhb6axC7OY8wC3dZQlWkTvEJtnD0Xrp5HBQ75YOc5lY1YVxJhMtXMDcxWWmwAzgdmktWjzFXAqfWYIaWKxyhG6Mgi46iy2ooNWcdgKW77QVqdQvpvqYsk/s1600/classuvm__report__catcher__inherit__graph.png" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em; text-align: justify;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhqIlUQER4QlPi9XhfaQjzlCKeQhb6axC7OY8wC3dZQlWkTvEJtnD0Xrp5HBQ75YOc5lY1YVxJhMtXMDcxWWmwAzgdmktWjzFXAqfWYIaWKxyhG6Mgi46iy2ooNWcdgKW77QVqdQvpvqYsk/s1600/classuvm__report__catcher__inherit__graph.png" /></a></div>
<div style="text-align: justify;">
Today we will look into a very useful concept of UVM specially when we are doing any erroneous testing. Its all about modifying the severity, id, action, verbosity or the report string itself before the report is finally issued by the report server. </div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
Normally in our test environment shout for error when any erroneous scenario like CRC error condition or generation of any error interrupt occurs. And we also write erroneous tests to test these scenarios where we end-up with error messages and tests fails. </div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div>
<div style="text-align: justify;">
The <i>uvm_report_catcher</i> is used to catch messages issued by the uvm report server. Upon catching a report, the catch method can modify the severity, id, action, verbosity or the report string itself before the report is finally issued by the report server. The report can be immediately issued from within the catcher class by calling the issue method.</div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
The catcher maintains a count of all reports with FATAL, ERROR or WARNING severity and a count of all reports with FATAL, ERROR or WARNING severity whose severity was lowered. These statistics are reported in the summary of the <i>uvm_report_server</i>.</div>
</div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
<b>Example: </b></div>
</div>
<div>
<div style="text-align: justify;">
<b><br /></b></div>
</div>
<div>
<div style="text-align: justify;">
<b>Report catcher class:</b></div>
</div>
<div>
<div>
<div style="text-align: justify;">
class error_report_catcher extends uvm_report_catcher;</div>
</div>
<div>
<div style="text-align: justify;">
//new constructor</div>
</div>
<div>
<div style="text-align: justify;">
virtual function action_e catch();</div>
</div>
<div>
<div style="text-align: justify;">
if(get_severity() == UVM_ERROR && get_id() == "MON_CHK_NOT_VALID") begin</div>
</div>
<div>
<div style="text-align: justify;">
set_severity(UVM_INFO);</div>
</div>
<div>
<div style="text-align: justify;">
return CAUGHT;</div>
</div>
<div>
<div style="text-align: justify;">
end</div>
</div>
<div>
<div style="text-align: justify;">
else begin</div>
</div>
<div>
<div style="text-align: justify;">
return THROW;</div>
</div>
<div>
<div style="text-align: justify;">
end</div>
</div>
<div>
<div style="text-align: justify;">
endfunction</div>
</div>
<div>
<div style="text-align: justify;">
endclass : error_report_catcher_c</div>
</div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
<b>Use of error catcher in testcase: </b></div>
</div>
<div>
<div style="text-align: justify;">
class erroneous_test extends base_test_class;</div>
</div>
<div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
// report catcher to suppress errors</div>
</div>
<div>
<div style="text-align: justify;">
error_report_catcher error_catcher ;</div>
</div>
<div>
<div style="text-align: justify;">
/// \fn new_constructor</div>
</div>
<div>
<div style="text-align: justify;">
</div>
</div>
<div>
<div style="text-align: justify;">
/// \fn build_phase</div>
</div>
<div>
<div style="text-align: justify;">
virtual function void build_phase(uvm_phase phase);</div>
</div>
<div>
<div style="text-align: justify;">
super.build_phase(phase);</div>
</div>
<div>
<div style="text-align: justify;">
error_catcher = new();</div>
</div>
<div>
<div style="text-align: justify;">
uvm_report_cb::add(null,error_catcher) ;</div>
</div>
<div>
<div style="text-align: justify;">
uvm_config_db#(int)::set(this,“uvc.tx_agent","is_active",UVM_ACTIVE);</div>
</div>
<div>
<div style="text-align: justify;">
</div>
</div>
<div>
<div style="text-align: justify;">
// User configurations</div>
</div>
<div>
<div style="text-align: justify;">
env_cfg.print();</div>
</div>
<div>
<div style="text-align: justify;">
uvm_config_db#(env_config_c)::set(this, "*" , “env_cfg", env_cfg);</div>
</div>
<div>
<div style="text-align: justify;">
// Calling the error sequence</div>
</div>
<div>
<div style="text-align: justify;">
uvm_config_db#(uvm_object_wrapper)::set(this, “uvc.tx_agent.tx_sequencer.main_phase","default_sequence",valid_invalid_seq_c::type_id::get());</div>
</div>
<div>
<div style="text-align: justify;">
endfunction : build_phase</div>
</div>
<div>
<div style="text-align: justify;">
<br /></div>
</div>
<div>
<div style="text-align: justify;">
endclass : erroneous_test</div>
</div>
</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-69971352068393942212016-09-11T06:42:00.000-07:002016-09-11T06:42:59.032-07:0064 core processor from Chinese chip maker Phytium<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjCzBaDzLsZ91xljgp5oGcH6aQ5koAld2FuRA_vxjeR6rt8dmQBZ360-v2OOCnmFny29Ecyzxsb__u5brJeuRkQmTo9I8VS4v24Xwd3HxscjpifYiTiS8uTtr383QZ7dMw8h-VBQvwLQUcH/s1600/PHYTIUM_64_core_processor.jpg" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"><img border="0" height="212" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjCzBaDzLsZ91xljgp5oGcH6aQ5koAld2FuRA_vxjeR6rt8dmQBZ360-v2OOCnmFny29Ecyzxsb__u5brJeuRkQmTo9I8VS4v24Xwd3HxscjpifYiTiS8uTtr383QZ7dMw8h-VBQvwLQUcH/s320/PHYTIUM_64_core_processor.jpg" width="320" /></a></div>
While the world awaits the AMD K12 and Qualcomm Hydra ARM server chips to join the ranks of the Applied Micro X-Gene and Cavium ThunderX processors already in the market, it could be upstart Chinese chip maker Phytium Technology that gets a brawny chip into the field first and also gets traction among actual datacenter server customers, not just tire kickers.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Phytium Technology has announced a 64-core ARM server CPU, which according to the press release will deliver 512 gigaflops of performance. The new chip, known as FT-2000/64, is aimed at “high throughput and high performance servers.”</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Phytium is a chip design enterprise, based in Tianjin, China. In March 2015, the company released its first products: the FT-1500A/4 and FT-1500A/16, 4-core and 16-core implementations, respectively of the ARMv8 design.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Phytium was on hand at last week’s Hot Chips 28 conference, showing off its chippery and laptop, desktop and server machines employing its “Earth” and “Mars” FT series of ARM chips. Most of the interest that people showed in the server variants, which are both based on variants of the “Xiaomi” core design that the company has cooked up based on ARMv8 intellectual property licensed from ARM Holdings. There is chatter that one of the three Chinese exascale machines, which we wrote about here, will employ a future Phytium processor, but we were unable to confirm this with the Phytium executives at the event. What we can tell you is that the first engineering samples of the two Earth ARM chips, the FT-1500A/4 and the FT-1500A/16, as well as the one Mars ARM chip, the FT-2000/64, are back from Taiwan Semiconductor Manufacturing Corp and that we saw systems running the Kylin Linux operating system (a variant of Canonical’s Ubuntu) at the Hot Chips event.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Here are the key chip features from the FT-2000/64 product page: </div>
<br />
<ul style="text-align: left;">
<li style="text-align: justify;">Process:Manufacturing with 28nm process</li>
<li style="text-align: justify;">Core:Integrating sixty-four FTC661 cores</li>
<li style="text-align: justify;">Frequency:Running at 1.5GHz~2.0GHz</li>
<li style="text-align: justify;">Cache:Integrating 32MB L2 cache and extending 128MB LLC</li>
<li style="text-align: justify;">Extension Interface:Integrating eight proprietary extension interfaces, each delivering 19.2GB/s effective r/w bandwidth</li>
<li style="text-align: justify;">Memory Interface:Extending sixteen DDR3-1600 memory controllers, which can deliver 204.8GB/s memory access bandwidth.</li>
<li style="text-align: justify;">I/O Interface:Integrating two x16 or four x8 PCIE Gen3 interface</li>
<li style="text-align: justify;">Power:Max. power 100W</li>
<li style="text-align: justify;">Package:FCBGA package with 2892 pins</li>
</ul>
<span style="text-align: justify;">No pricing was provided on the new chips, and it’s unclear from the press release if the product is available today. The next time we hear about the FT-2000/64 might very well be when it shows up in a TOP500 supercomputer. Stay tuned.</span></div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-53063309973511187532016-09-11T04:28:00.000-07:002016-09-11T04:28:58.581-07:004μm thick fabric like flexible circuit<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiQagG3MBI0LNaRZzbnGZ26Z3RIcLAgtjNRjBTTOhVtarm_ark0LlrIDibhbf-Tl0L4bhrnDZizcAlIETTj6_b6dPxuEvOU4d4ZnyuPxVIBgHoQ3JkJVhdf9qmJ4g5PE1FOK2jW8wPx4on-/s1600/KAIST-flexible-circuit-has-oxide-transistors.jpg" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"><img border="0" height="239" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiQagG3MBI0LNaRZzbnGZ26Z3RIcLAgtjNRjBTTOhVtarm_ark0LlrIDibhbf-Tl0L4bhrnDZizcAlIETTj6_b6dPxuEvOU4d4ZnyuPxVIBgHoQ3JkJVhdf9qmJ4g5PE1FOK2jW8wPx4on-/s320/KAIST-flexible-circuit-has-oxide-transistors.jpg" width="320" /></a></div>
<div style="text-align: justify;">
According to the Korea Advanced Institute of Science and Technology (KAIST), complete with substrate, an active matrix for a flexible display need only be 4μm thick. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Initially on a sacrificial laser-reactive substrate the matrix of ultra-thin n-type transparent oxide thin-film transistors (TFTs) were fabricated for the back plane.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Laser irradiation from the backside of the substrate split off only the oxide TFT array as a result of reaction with the laser-reactive layer.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The free transistors were transferred to a 4μm polyethylene terephthalate (PET) substrate, and then the combination was further transferred con-formally to the surface of human skin and artificial leather to demonstrate the possibility of the wearable application.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
“The attached oxide TFTs showed high optical transparency of 83% and 40cm2/Vs even under several cycles of severe bending tests,” said KAIST.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The method is called inorganic-based laser lift-off (ILLO).</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
“By using our ILLO process, the technological barriers for high performance transparent flexible displays have been overcome at a relatively low cost by removing expensive polyimide substrates. Moreover, the high-quality oxide semiconductor can be easily transferred onto skin-like, or any flexible, substrate for wearable application,” said Professor Keon Jae Lee.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Con-formal displays are a potential application.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
“With the advent of the Internet of Things era, demand has grown for wearable and transparent displays that can be applied to fields such as augmented reality and skin-like thin flexible devices,” said KAIST. “However, previous flexible transparent displays have poor transparency and low electrical performance. To improve the transparency and performance, past research efforts have tried to use inorganic-based electronics, but the fundamental thermal instabilities of plastic substrates have hampered the high temperature process, an essential step necessary for the fabrication of high performance electronic devices.”</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0Bengaluru, Karnataka 560001, India12.9715987 77.59456269999998312.4764182 76.949115699999979 13.4667792 78.240009699999987tag:blogger.com,1999:blog-4978237314452270227.post-77285222657997574992016-07-18T09:36:00.000-07:002016-07-18T09:37:40.485-07:00Mega Processor to Understand Micro Processor<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiYck7YdPKW_i69L_apqQFtQM4XdDjy0lzWyehGgl5D5GEEVqOa1hN8qRAvsDXt6CdzSqcLrTggQWwu-tPK5M2SFn7fK-Eidq8Mn-G7E_Ve6bA8cG59LIJw4AOZLgC1XG5UQ5jwMZaLUYSS/s1600/megaprocessor-panorama.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img alt="MegaProcessor Panaroma Image" border="0" height="204" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiYck7YdPKW_i69L_apqQFtQM4XdDjy0lzWyehGgl5D5GEEVqOa1hN8qRAvsDXt6CdzSqcLrTggQWwu-tPK5M2SFn7fK-Eidq8Mn-G7E_Ve6bA8cG59LIJw4AOZLgC1XG5UQ5jwMZaLUYSS/s640/megaprocessor-panorama.jpg" title="Mega Processor" width="640" /></a></div>
<br />
Have you ever imagine how the work or what's going on inside? Think about a bigger version of a microprocessor where you can walk inside and look how it is working in real.<br />
<br />
You may have heard that your smartphone contains more computing power than all the computers used on the Apollo mission combined. But imagine taking the computing power of a Super Nintendo, and packing it into a computer the size of--a living room?<br />
<br />
The "mega-processor" is essentially a blown up version of a tiny chip that allows you to see how all the elements of a computer chip join together and how it actually works.<br />
<br />
A Cambridge resident has finished building a 10-metre wide and 2-metre high computer in his living room, which he uses to play the video game Tetris.<br />
<br />
James Newman took four years and £40,000 to build the processor which works exactly like a small microprocessor chip in a regular desktop computer or laptop that's about the size of a sim card.<br />
<br />
This room-sized megaprocessor has 40,000 transistors, 10,000 LED lights, weighs around half a tonne (500kg) and burns 500W of electricity, according to Newman, who explains the entire contraption in a video.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<iframe allowfullscreen="" class="YOUTUBE-iframe-video" data-thumbnail-src="https://i.ytimg.com/vi/z71h9XZbAWY/0.jpg" frameborder="0" height="360" src="https://www.youtube.com/embed/z71h9XZbAWY?feature=player_embedded" width="480"></iframe></div>
<br />
<br />
James Newman said his Mega Processor relies almost entirely on the hand-soldered components, and will ultimately demonstrate how data travels through and is processed in a simple CPU core. He's just finished putting together the general purpose registers, and in May completed the arithmetic and logic unit.<br />
<br />
Each transistor acts like a digital switch, and can be chained together to form huge decision-making circuits that execute software, instruction by instruction.<br />
<br />
Newman, whose background is in software development and FPGA programming, told The Register he has spent about £40k on the project to date. He started planning the processor in 2012, and began building the beast a year later.</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-80400259647287558102016-07-04T00:08:00.000-07:002016-07-04T00:08:13.829-07:00The World's First 1,000 Processor Chip ( KiloCore Chip )<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEifjSpZrBlUQfPbUlfEGA__UyYRfTfDIamK-URwkAEWJj96ODzlQgehyphenhyphenk6zYAgpZaFof3i_HaZGAg1BSpJ0bYZn2vZH7gZMdPlvi6LumQM6GeAhAaHXSJ3lYvaTVMBxaOVDRnSsM7EAU2Gp/s1600/kilocore_chip.jpg" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEifjSpZrBlUQfPbUlfEGA__UyYRfTfDIamK-URwkAEWJj96ODzlQgehyphenhyphenk6zYAgpZaFof3i_HaZGAg1BSpJ0bYZn2vZH7gZMdPlvi6LumQM6GeAhAaHXSJ3lYvaTVMBxaOVDRnSsM7EAU2Gp/s1600/kilocore_chip.jpg" width="320" /></a></div>
<div class="MsoNormal" style="text-align: justify;">
A team of scientists from the
University of California has created the world's first microchip with 1,000
independent processors. Called 'KiloCore' chip, it is also claimed to be the
world's fastest chip ever designed at a university. The chip, which was
presented this week at the 2016 Symposium on VLSI Technology and Circuits, is
capable of 1.78 trillion instructions per second and contains 621 million
transistors. The partially Department of Defense-funded KiloCore chip was
ultimately built by IBM using existing 32 nanometer semiconductor fabrication
technology.<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
Unfortunately, a 1,000 core chip
isn't something that could just be plugged into the next line of MacBook Pros.
It wouldn't even really suffice as a graphics processor, where massively
parallel computation is the norm. In fact, many GPUs exceed the 1,000 cores of
the UC Davis chip, but with the caveat that the individual cores are directed
according to a central controller. The KiloCore, by contrast, is built from
completely independent cores capable of running completely independent computer
programs.<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
Here's all you need to know about
the chip:<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
</div>
<ul>
<li>This microchip has been designed
by a team at the University of California, Davis, Department of Electrical and
Computer Engineering.</li>
<li>KiloCore chip executes
instructions more than 100 times more efficiently than a modern laptop
processor.</li>
<li>Each processor core can run its
own small program independently of the others, which is a fundamentally more
flexible approach than the Single-Instruction-Multiple-Data approaches utilized
by processors such as graphics processing unit (GPU). Because each processor is
independently clocked, it can shut itself down to further save energy when not
needed.</li>
<li>The chip has been fabricated by
IBM using its 32nm CMOS technology. KiloCore's each processor core can run its
own small program independently of the others.</li>
<li>Cores operate at an average
maximum clock frequency of 1.78 GHz, and they transfer data directly to each
other rather than using a pooled memory area that can become a bottleneck for
data.</li>
</ul>
<o:p></o:p><br />
<div class="MsoNormal" style="text-align: justify;">
<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
The independence of the cores
makes the KiloCore chip a multiple instruction multiple data (MIMD) computer.
This is in contrast to the more typical single instruction multiple data (SIMD)
variety of parallel computation, as would be expected in a graphics processor.
A SIMD machine's version of parallelism is to implement the same single operation
across many different cores - that is, do the same thing to many different
units of data. This is the norm in image processing, for example, where a lot
of different pixels holding different a lot of different values are all updated
in the same way. A MIMD machine can be expected to do much more complex
calculations.</div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
Together, the 1,000 processors
can execute 115 billion instructions per second while dissipating only 0.7
Watts. As noted in a UC Davis press release, this power requirement is low
enough that it could be supplied by a single AA battery, achieving an
efficiency of around 100 times that of a normal laptop processor.<o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<br />
<div class="MsoNormal" style="text-align: justify;">
The energy savings here largely
has to do with the abandoning of the traditional system memory architecture, in
which data for multiple cores is stored in a central RAM unit. Rather than
sharing data in this way, the KiloCore chip uses a built-in networking scheme
in which data is transferred directly between the different processors using
packet- and circuit-switched networking.<o:p></o:p></div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-87232386117273210222016-01-22T02:45:00.000-08:002016-09-10T02:57:21.984-07:00Radix number systems and conversions<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
We have learned and use the decimal numbering system simply because humans are born with ten fingers! Hence, the numeric system we is the decimal number system, but this system is not convenient for machines since the information is handled codified in the shape of <b>ON</b> or <b>OFF</b> bits.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
This means, we have to learn the binary system in addition to the decimal system. We also will discuss the octal and hexadecimal systems because conversion to/from binary is easy and numbers in these systems are easier to read than binary numbers for humans. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
This way of codifying takes us to the necessity of knowing the positional methods of calculation which will allow us to express a number in any base where we need it.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
A base of a number system or radix defines the range of values that a digit may have.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Binary Number System</b></div>
<div style="text-align: justify;">
In the binary system or <b>base 2</b>, there can be only two values for each digit of a number, either a "0" or a "1".</div>
<div style="text-align: justify;">
Digital and computer technology is based on the binary number system, since the foundation is
based on a transistor, which only has two states: on or off.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Each digit of the number is called a bit or which is a short for binary digits.</div>
<div style="text-align: justify;">
</div>
<ul>
<li>An 8-bit group is referred to as a <b>Byte</b></li>
<li>An 4-bit group is referred to as a <b>nibble</b></li>
</ul>
<br />
<div style="text-align: justify;">
Each bit is weighted based on its position in the sequence (powers of 2) from the <b>Least</b></div>
<div style="text-align: justify;">
<b>Significant Bit (LSB)</b> to the <b>Most Significant Bit (MSB)</b>.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Each bit must be less than 2 which means it has to be either 0 or 1.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
For example (1010.11)2 is evaluated as:</div>
<div style="text-align: justify;">
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhlTOj6O_8aVKSVK_N_jsX8na-gsXpDSS5pihj7KcjDjJpKvbUMJTYtFbe1me_5jBvH9OwZDC4bJuFGO32RaaD4kfjtlQt3cEH9-OtQvBse2pF8nd-CmdDXRQVW6uMWXeNlnqJETAoE2mub/s1600/Radiax_number_system-binary.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="78" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhlTOj6O_8aVKSVK_N_jsX8na-gsXpDSS5pihj7KcjDjJpKvbUMJTYtFbe1me_5jBvH9OwZDC4bJuFGO32RaaD4kfjtlQt3cEH9-OtQvBse2pF8nd-CmdDXRQVW6uMWXeNlnqJETAoE2mub/s400/Radiax_number_system-binary.JPG" width="400" /></a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
(1010.11)2 = 8 + 0 + 2 + 0 + 0.5 + 0.25 = (10.75)10 </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Note: The general term for decimal point is radix point</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
In binary, the count starts at 0 (called <b>0-referencing</b>), where in decimal, the count typically starts</div>
<div style="text-align: justify;">
with 1 (called <b>1-referencing</b>) </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Octal Number System</b></div>
<div style="text-align: justify;">
In the octal system or <b>base 8</b>, there can be eight choices for each digit of a number:</div>
<div style="text-align: justify;">
"0", "1", "2", "3", "4", "5", "6", "7".<br />
<br />
Octal number systems are used by humans as a representation of long strings of bits since they are:</div>
<div style="text-align: justify;">
<br />
<ul>
<li>Easier to read and write, for example 347 in octal is easier to read and write than 011100111 in binary.</li>
<li>Easy to convert (Groups of 3 or 4)</li>
<li>The most common way is to use Hex to write the binary equivalent; two hexadecimal digits make a Byte (groups of 8-bit), which are basic blocks of data in Computers.</li>
</ul>
<br />
<b>Decimal Number System</b></div>
<div style="text-align: justify;">
In the decimal system or <b>base 10</b>, there are ten different values for each digit of a number:</div>
<div style="text-align: justify;">
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9".<br />
<br />
Decimal number system is default and easy to use for us. For example when you see a number 56 your assumption is that its base or radix is 10 i.e. “56 base 10”.<br />
<br />
<ul>
<li>Each digit is weighted based on its position in the sequence (power of 10) from the Least
Significant Digit (LSD, power of 0) to the Most Significant Digit (MSD, highest power).
</li>
<li>Each digit must be less than 10 (0 to 9) </li>
</ul>
</div>
<div style="text-align: justify;">
<b>Hexadecimal Number System</b></div>
<div style="text-align: justify;">
In the hexadecimal system, we allow 16 values for each digit of a number:</div>
<div style="text-align: justify;">
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "A", "B", "C", "D", "E", and "F".</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Where “A” stands for 10, “B” for 11 and so on.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Conversion among different radices</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>1. Convert from Decimal to Any Base</b></div>
<div style="text-align: justify;">
Let’s think about what you do to obtain each digit. As an example, let's start with a decimal number 1234 and convert it to decimal notation. To extract the last digit, you move the decimal point left by one digit, which means that you divide the given number by its base 10.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
1234/10 = 123 + 4/10</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The remainder of 4 is the last digit. To extract the next last digit, you again move the decimal point left by one digit and see what drops out.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
123/10 = 12 + 3/10</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The remainder of 3 is the next last digit. You repeat this process until there is nothing left. Then you stop. In summary, you do the following: </div>
<div style="text-align: justify;">
<br /></div>
<div class="separator" style="clear: both; text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgatDjCM1-5Qbg0dK8AIoPvVHJbYhIaSvbzsbHymonXFdoV35VY6mJNPU9YvjIjYfOTiZiDcTT8BTlleoJqg7_gu5optLAqqKTQUZbIIlgjvWdw7SYTcGPLRK8zcjqR0Xhx9WdYI7hrep_5/s1600/Radiax_number_system-1.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="140" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgatDjCM1-5Qbg0dK8AIoPvVHJbYhIaSvbzsbHymonXFdoV35VY6mJNPU9YvjIjYfOTiZiDcTT8BTlleoJqg7_gu5optLAqqKTQUZbIIlgjvWdw7SYTcGPLRK8zcjqR0Xhx9WdYI7hrep_5/s640/Radiax_number_system-1.JPG" width="640" /></a></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
<b>Conversion of decimal number to binary</b></div>
<div style="text-align: justify;">
Now, let's try a nontrivial example. Let's express a decimal number <b>1341</b> in binary notation. </div>
<div style="text-align: justify;">
Note that the desired base is <b>2</b>, so we repeatedly divide the given decimal number by <b>2</b>. </div>
<div style="text-align: justify;">
<br /></div>
<div class="separator" style="clear: both; text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiWdlHRzs9XNyMgmC2lGx7dI7rLab7PMmvr3ZtVMv_kqOUHICUP9nTHYXguhYxs5if7O9M2oz6jOpTO-SLWNQ23-dzZ7GIwKnGM1GFx_wAiUoP37mmpDEyL0tTGCX4Iz-F-87WeMU-faC-F/s1600/Radiax_number_system-2.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="286" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiWdlHRzs9XNyMgmC2lGx7dI7rLab7PMmvr3ZtVMv_kqOUHICUP9nTHYXguhYxs5if7O9M2oz6jOpTO-SLWNQ23-dzZ7GIwKnGM1GFx_wAiUoP37mmpDEyL0tTGCX4Iz-F-87WeMU-faC-F/s640/Radiax_number_system-2.JPG" width="640" /></a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Conversion of decimal number to octal</b></div>
<div style="text-align: justify;">
Now, let's express the same decimal number 1341 in octal notation. </div>
<div style="text-align: justify;">
<br /></div>
<div class="separator" style="clear: both; text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjcRAwICESofwtQVB6wh1DrDLKFtc-b1I1qXQSy4QvfUfrbwEObldZxjgW-ZQTmOjfHIEOJ6DMESUPM21-e53hqNItvGXS2aWVI1wq93bRFr3ZqlN8xvFtk40fZNJIUcn4fpx7YNeONICBk/s1600/Radiax_number_system-3.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="152" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjcRAwICESofwtQVB6wh1DrDLKFtc-b1I1qXQSy4QvfUfrbwEObldZxjgW-ZQTmOjfHIEOJ6DMESUPM21-e53hqNItvGXS2aWVI1wq93bRFr3ZqlN8xvFtk40fZNJIUcn4fpx7YNeONICBk/s640/Radiax_number_system-3.JPG" width="640" /></a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Conversion of decimal number to hexadecimal</b></div>
<div style="text-align: justify;">
Let's express the same decimal number 1341 in hexadecimal notation. </div>
<div style="text-align: justify;">
<br /></div>
<div class="separator" style="clear: both; text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhRPXPvYs-68azSHP4V9JhPiFg6cfGVVRfpfHrw8IiMh1VWSqTljsp4b7Ia1EZeN7jE0_elp8G6lQxJbnM0UrmEBuV9AgyAAZlrIhhrL7yHjOZwY0GXct14k-jqAd5WYsgNUjRzKes767Z5/s1600/Radiax_number_system-4.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="140" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhRPXPvYs-68azSHP4V9JhPiFg6cfGVVRfpfHrw8IiMh1VWSqTljsp4b7Ia1EZeN7jE0_elp8G6lQxJbnM0UrmEBuV9AgyAAZlrIhhrL7yHjOZwY0GXct14k-jqAd5WYsgNUjRzKes767Z5/s640/Radiax_number_system-4.JPG" width="640" /></a></div>
<div style="text-align: justify;">
The easiest way to convert fixed point numbers to any base is to convert each part separately. We begin by separating the number into its integer and fractional part. The integer part is converted using the remainder method, by using a successive division of the number by the base until a zero is obtained. At each division, the reminder is kept and then the new number in the base r is obtained by reading the remainder from the lat remainder upwards.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The conversion of the fractional part can be obtained by successively multiplying the fraction with the base. If we iterate this process on the remaining fraction, then we will obtain successive significant digit. This methods form the basis of the multiplication methods of converting fractions between bases.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Example:</b></div>
<div style="text-align: justify;">
Convert the decimal number 3315 to hexadecimal notation. What about the hexadecimal equivalent of the decimal number 3315.3? </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Solution:</b></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgmLRslWLaXAujqgHi57DC7_6VmCjoawrxAmTx5ZR9z1zKQ4AUz9s9Ss8t_4uTeRyipxMdAd16OXqGHO4PG0pqIa3T9MsglXgbc4EoOpoc8APbaJSRKypvlyVxzZILcfb4tzII1kIvLzoJM/s1600/Radiax_number_system-5.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="354" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgmLRslWLaXAujqgHi57DC7_6VmCjoawrxAmTx5ZR9z1zKQ4AUz9s9Ss8t_4uTeRyipxMdAd16OXqGHO4PG0pqIa3T9MsglXgbc4EoOpoc8APbaJSRKypvlyVxzZILcfb4tzII1kIvLzoJM/s640/Radiax_number_system-5.JPG" width="640" /></a></div>
<div style="text-align: justify;">
<br />
<b>Conversion of Any Base to Decimal</b><br />
Let's try to understand what a decimal number means. For example, 1234 means that there are four boxes (digits); and there are 4 one's in the right-most box (least significant digit), 3 ten's in the next box, 2 hundred's in the next box, and finally 1 thousand's in the left-most box (most significant digit). The total is 1234:<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiavuagFfFW0_wuW9USvhDOeuI4w8cNzR7rGpG4vv3lyw5DzS3PPvPWkmaAfkSjSZ5qU4eKtAmaiHPEGudHHe1mEIZhRniDNAbMkyOvlbgD2VsO4CJaLTZ3sDiWILkhDbYv4jiBKvLNMKB6/s1600/decimal+number.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="95" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiavuagFfFW0_wuW9USvhDOeuI4w8cNzR7rGpG4vv3lyw5DzS3PPvPWkmaAfkSjSZ5qU4eKtAmaiHPEGudHHe1mEIZhRniDNAbMkyOvlbgD2VsO4CJaLTZ3sDiWILkhDbYv4jiBKvLNMKB6/s400/decimal+number.JPG" width="400" /></a></div>
<br />
or simply, 1*1000 + 2*100 + 3*10 + 4*1 = 1234<br />
<br />
Thus, each digit has a value: 10^0
=1 for the least significant digit, increasing to 10^1
=10, 10^2
=100, 10^3
=1000, and so
forth.<br />
<br />
Likewise, the least significant digit in a hexadecimal number has a value of<br />
<br />
16^0 =1 for the least significant digit, increasing to<br />
16^1 =16 for the next digit,<br />
16^2 =256 for the next,<br />
16^3 =4096 for the next, and so forth.<br />
<br />
Thus, 1234 means that there are four boxes (digits); and there are 4 one's in the right-most box (least significant digit), 3 sixteen's in the next box, 2 256's in the next, and 1 4096's in the left-most box (most significant digit). The total is:<br />
<br />
1*4096 + 2*256 + 3*16 + 4*1 = 4660<br />
<br />
In summary, the conversion from any base to base 10 can be obtained from the formulae<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjSi91XajnRzt0Y7cfd_sNjRuufxPrV9esDWrzoiMs1QcM1lAc7FrYtILn0v6fraD3BJnNMFHoX3o4jJd822UiHmt9x7AdNm1WAEXdZlMhp_7EANhSNXFiFbegRRUUgoR00sjZ8z7mkhD4a/s1600/decimal+conversion+formulae.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjSi91XajnRzt0Y7cfd_sNjRuufxPrV9esDWrzoiMs1QcM1lAc7FrYtILn0v6fraD3BJnNMFHoX3o4jJd822UiHmt9x7AdNm1WAEXdZlMhp_7EANhSNXFiFbegRRUUgoR00sjZ8z7mkhD4a/s1600/decimal+conversion+formulae.JPG" /></a></div>
<br />
Where b is the base, di the digit at position i, m the number of digit after the decimal point, n the number of digits of the integer part and X10 is the obtained number in decimal. This form the basic of the polynomial method of converting numbers from any base to decimal<br />
<br />
<b>Example:</b> Convert 234.14 expressed in an octal notation to decimal.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgBYUj3XPrJJqOl24-hLYJTDlcmrpNp1BkW_Giw-Oj_5GXS2uqhejRLnJ48WRSfn11okZZg7v2e_aFjbQtLj7zTKZ4LDJ7mnxbaQTcga-rNckSChJQuOJvokdFYijkpFBAL8J9s7zBgsDqK/s1600/octal_to_decimal.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="24" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgBYUj3XPrJJqOl24-hLYJTDlcmrpNp1BkW_Giw-Oj_5GXS2uqhejRLnJ48WRSfn11okZZg7v2e_aFjbQtLj7zTKZ4LDJ7mnxbaQTcga-rNckSChJQuOJvokdFYijkpFBAL8J9s7zBgsDqK/s640/octal_to_decimal.JPG" width="640" /></a></div>
<br />
<b>Example:</b> Convert the hexadecimal number 4B3 to decimal notation. What about the decimal equivalent of the hexadecimal number 4B3.3?<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgaGZubSiIv_Fnn4ygFGnCUWdZbPnhMVudAPNAtRj6puNGyt1iPUoxx5uA5lTRCpzRo7brEzg56W96prBacWPp4hyphenhyphenUkVADQZU9r8sawwGmNmEyyjvL88QCO35iShetESieD6dUDO2tqXe1o/s1600/hexadecimal_to_decimal.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="120" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgaGZubSiIv_Fnn4ygFGnCUWdZbPnhMVudAPNAtRj6puNGyt1iPUoxx5uA5lTRCpzRo7brEzg56W96prBacWPp4hyphenhyphenUkVADQZU9r8sawwGmNmEyyjvL88QCO35iShetESieD6dUDO2tqXe1o/s640/hexadecimal_to_decimal.JPG" width="640" /></a></div>
<br />
<b>Example:</b> Convert 234.14 expressed in an octal notation to decimal.<br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjkGJ8ncsLwauyrSbzQXCW8Iv6YkltC84p3VysqbCfpigIkWvfCBRWtKBfIYlhFjkUKsc1ktpcD49yC6BNzf1g8ZlF33EJK0AWJSJ2rGP2ZFI2GFIB8Pge8SNDfivAT2hTuYImXEALyVoAO/s1600/octal_to_decimal1.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="105" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjkGJ8ncsLwauyrSbzQXCW8Iv6YkltC84p3VysqbCfpigIkWvfCBRWtKBfIYlhFjkUKsc1ktpcD49yC6BNzf1g8ZlF33EJK0AWJSJ2rGP2ZFI2GFIB8Pge8SNDfivAT2hTuYImXEALyVoAO/s640/octal_to_decimal1.JPG" width="640" /></a></div>
<br /></div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0Bengaluru, Karnataka 560001, India12.9715987 77.59456269999998312.4764182 76.949115699999979 13.4667792 78.240009699999987tag:blogger.com,1999:blog-4978237314452270227.post-15043335732105770602015-11-10T11:08:00.005-08:002021-05-04T05:02:03.523-07:00UVM Interview Questions - 5<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<b>Q31: What is virtual sequencer and virtual sequence in UVM?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
A virtual sequencer is a sequencer that is not connected to a driver itself, but contains handles for sequencers in the testbench hierarchy. It is an optional component for running of virtual sequences - optional because they need no driver hookup, instead calling other sequences which run on real sequencers.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
A sequence which controls stimulus generation across more than one sequencer, coordinate the stimulus across different interfaces and the interactions between them. Usually the top level of the sequence hierarchy i.e. 'master sequence' or 'coordinator sequence'. Virtual sequences do not need their own sequencer, as they do not link directly to drivers. When they have one it is called a virtual sequencer.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Here is a good article which explains how to use virtual sequence and virtual sequencer.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
http://www.learnuvmverification.com/index.php/2016/02/23/how-virtual-sequence-works-part-1/</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q32: How set_config_* works?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The <i>uvm_config_db</i> class provides a convenience interface on top of the uvm_resource_db to simplify the basic interface that is used for configuring uvm_component instances.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Configuration is a mechanism in UVM that higher level components in a hierarchy can configure the lower level components variables. Using <b><i>set_config_*</i></b> methods, user can configure integer, string and objects of lower level components. Without this mechanism, user should access the lower level component using hierarchy paths, which restricts re-usability.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
This mechanism can be used only with components. Sequences and transactions cannot be configured using this mechanism. When <b><i>set_config_*</i></b> method is called, the data is stored w.r.t strings in a table. There is also a global configuration table.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Higher level component can set the configuration data in level component table. It is the responsibility of the lower level component to get the data from the component table and update the appropriate table.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
following are the method to configure integer, string and object of uvm_object based class respectively.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
function void <b>set_config_int</b> (string inst_name, string field_name, uvm_bitstream_t value)</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
function void <b>set_config_string</b> (string inst_name, string field_name, string value)</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
function void <b>set_config_object</b> (string inst_name, string field_name, uvm_object value, bit clone = 1)</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q33: What are the advantages of uvm RAL model ?</b></div>
<br />
<ul style="text-align: left;">
<li style="text-align: justify;">The RAL (register abstraction layer) provides accesses to DUT and also keeps a track of register content of DUT.</li>
<li style="text-align: justify;">UVM RAL can be used to automate the creation of high level, object oriented abstraction model of registers and memory in DUT.</li>
<li style="text-align: justify;">Register layer makes the register abstraction and access of its contents independent of the bus protocol which is used to transfer data in and out of registers inside the design.</li>
<li style="text-align: justify;">Hierarchical model provided by RAL makes the reusability of test bench components very easy.</li>
<li style="text-align: justify;">The changes in initial configuration of registers or specifications can be easily communicated in the entire environment. RAL layer supports both front door and backdoor access. The backdoor access does not use the bus interface rather it uses the HDL defined paths for direct communication with the device. Thus in zero simulation time the registers of device can be reconfigured using the backdoor access and verification can be started.</li>
<li style="text-align: justify;">One more advantage of backdoor access is that it can be used for verify if the access through front door are happening correctly. To achieve this the front door, write is verified using backdoor read.</li>
</ul>
<br />
<div>
<div style="text-align: justify;">
<b>Q34: What are the different override types?</b></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
Two type of overriding is supported by UVM</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>1. Type overriding</b></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
Type overriding means that every time a component class type is created in the Testbench hierarchy, a substitute type i.e. derived class of the original component class, is created in its place. It applies to all the instances of that component type.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Syntax:</div>
<div style="text-align: justify;">
<span style="font-family: "courier new", courier, monospace;"><original_type>::type_id::set_type_override(<substitute_type>::get_type(), replace);</span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
where “replace” is a bit which is when set equals to 1, enables the overriding of an existing override else existing override is honoured.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>2. Instance overriding</b></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
In Instance Overriding, as name indicates it substitutes ONLY a particular instance of the component OR a set of instances with the intended component. The instance to be substituted is specified using the UVM component hierarchy.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Syntax:</div>
<div style="text-align: justify;">
<span style="font-family: "courier new", courier, monospace;"><original_type>::type_id::set_inst_override(<substitute_type>::get_type(), <path_string>);</span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Where “path_string” is the hierarchical path of the component instance to be replaced.</div>
</div>
<div style="text-align: justify;">
<br /></div>
<div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
<span lang="EN"><b>Q35: Explain end of simulation in UVM?</b><o:p></o:p></span></div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
Different approaches to finish the UVM Test using
the objection mechanism are</div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
<span lang="EN">1. Raising & dropping objections<o:p></o:p></span></div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
<span lang="EN">raise_objection() and drop_objection() are the
methods to be used to do that.<o:p></o:p></span></div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
<span lang="EN">2. phase_ready_to_end <o:p></o:p></span></div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
<span lang="EN">phase_ready_to_end method is executed automatically
by UVM once ‘all dropped’ condition is achieved during Run Phase.<o:p></o:p></span></div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
<span lang="EN">3. set_drain_time <o:p></o:p></span></div>
<div class="MsoNormal" style="line-height: 115%; margin-bottom: 10pt; text-align: justify;">
<span lang="EN">Another approach supported by UVM is setting the
drain time for the simulation environment. Drain time concept is related to the
extra time allocated to the UVM environment to process the left over activities
e.g. last packet analysis & comparison etc after all the stimulus is
applied & processed.<o:p></o:p></span></div>
</div>
<div style="text-align: justify;">
<a href="http://www.vlsiencyclopedia.com/2015/09/uvm-interview-questions-4.html" rel="nofollow"><b style="background-color: white; font-family: "trebuchet ms", trebuchet, verdana, sans-serif; font-size: 15.4px;"><span style="font-size: x-large;"><span style="color: #888888;"><< PREVIOUS</span></span></b></a> <span face=""trebuchet ms", trebuchet, verdana, sans-serif" style="background-color: white; font-size: x-large; text-align: left;"><b><span style="color: blue;"></span></b></span><b><span style="font-size: x-large;"> <a href="http://www.vlsiencyclopedia.com/2021/05/uvm-interview-questions-6.html" rel="nofollow">NEXT >></a></span></b></div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-63983316522381761292015-10-05T05:58:00.000-07:002015-10-06T04:41:43.519-07:00IBM steps forward to replace Silicon Transistors with Carbon Nanotubes<div dir="ltr" style="text-align: left;" trbidi="on">
<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: right; margin-left: 1em; text-align: right;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjzGbaRJv04Nq4GsAl0yN4qDhlV1vTpjoE-_QPTaCWXuJG3o0cIBt2z8mnDqVbc_MKLfj6mSuzawCv_5b0QeuRUqckAh-BUiTQcZ9E-F9zZ9L7VX0RYTKvbBfrPNrB8nfBvt2i4I6ujE9PH/s1600/Carbon-Nanotubes.jpg" imageanchor="1" style="clear: right; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img alt="Carbon Nanotube" border="0" height="222" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjzGbaRJv04Nq4GsAl0yN4qDhlV1vTpjoE-_QPTaCWXuJG3o0cIBt2z8mnDqVbc_MKLfj6mSuzawCv_5b0QeuRUqckAh-BUiTQcZ9E-F9zZ9L7VX0RYTKvbBfrPNrB8nfBvt2i4I6ujE9PH/s400/Carbon-Nanotubes.jpg" title="Carbon Nanotube" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Carbon Nanotube</td></tr>
</tbody></table>
<div style="text-align: justify;">
The breakthrough is that - IBM improves carbon nanotube scaling below 10nm. How ever before calling it as breakthrough we should also check out what other giants like Intel, AMD, TSMC or Samsung is working on. This breakthrough has relation with the Moore's Law. Yes you got right..!!It says that the transistor counts double only every 18 month or so. It’s the time that <a href="http://www.vlsiencyclopedia.com/2011/11/intel-marks-40-years-of-4004.html">Intel marks 40 years of the 4004 microprocessor</a> and here now lying some fear that progress will soon hit a wall.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
You can refer to my post <a href="http://www.vlsiencyclopedia.com/2011/07/history-and-evolution-of-integrated.html">History and Evolution of Integrated Circuits</a> where it shows clear progress of semiconductor industry.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
But not to worry, IBM has developed a way that could help the semiconductor industry continue to make ever more dense chips to support Moore's law. These chips will be both faster and more power efficient.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Few glimpse of carbon nanotube transistors</b></div>
<br />
<ul style="text-align: left;">
<li style="text-align: justify;">Carbon nanotube transistors can operate at ten nanometers</li>
<li style="text-align: justify;">Equivalent to 10,000 times thinner than a strand of human hair</li>
<li style="text-align: justify;">Less than half the size of today’s leading silicon technology</li>
<li style="text-align: justify;">Could also mean wearables that attach directly to skin and internal organs</li>
</ul>
<br />
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Here I have an animation for <a href="http://www.vlsiencyclopedia.com/2013/08/animated-nanofactory-in-action.html">Animated Nanofactory in Action</a>.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
As a result of this the devices will become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
These results could overcome contact resistance challenges all the way to the <b>1.8 nanometer node</b> – four technology generations away.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
A project at IBM is now aiming to have transistors built using <b>carbon nanotubes ready to take over</b> from <b>silicon transistors soon after 2020</b>. According to the semiconductor industry’s roadmap, transistors at that point must have features as small as five nanometers to keep up with the continuous miniaturization of computer chips.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
IBM has previously shown that <b>carbon nanotube transistors</b> can operate as excellent switches at channel dimensions of <b>less than ten nanometers</b> – the equivalent to 10,000 times <b>thinner than a strand of human hair</b> and less than half the size of today’s leading silicon technology.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
IBM's new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Earlier this summer, IBM unveiled the<b> first 7 nanometer node silicon test chip</b>, pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its<b> $3 billion chip R&D investment announced in July 2014</b>.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
IBM’s chosen design uses six nanotubes lined up in parallel to make a single transistor. <b>Each nanotube is 1.4 nanometers wide, about 30 nanometers long</b>, and spaced roughly eight nanometers apart from its neighbors. Both ends of the six tubes are embedded into electrodes that supply current, leaving around <b>10 nanometers</b> of their lengths exposed in the middle. A third electrode runs perpendicularly underneath this portion of the tubes and switches the transistor on and off to represent digital 1s and 0s.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The IBM team has tested nanotube transistors with that design, but so far it hasn't found a way to position the nanotubes closely enough together, because existing chip technology can’t work at that scale. The favored solution is to chemically label the substrate and nanotubes with compounds that would cause them to self-assemble into position. Those compounds could then be stripped away, leaving the nanotubes arranged correctly and ready to have electrodes and other circuitry added to finish a chip.</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-47249164892746031412015-10-04T23:10:00.000-07:002015-10-04T23:10:51.197-07:00International Conference on VLSI Design and Embeded Systems - Jan 2016<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi54LK4mbWbxzheV-C6embn8hpwMig6ABzZ5cZ1XuLpLaYMipthhoS1DAwrinNUp5aKzBEdx9GLdqoGk562YXXpy-oJ1KzuwI_TrdAoUI7DEVNNd1I8VGLjYywQC4bBsbCPh3poFIyvL5OE/s1600/logo1.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="137" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi54LK4mbWbxzheV-C6embn8hpwMig6ABzZ5cZ1XuLpLaYMipthhoS1DAwrinNUp5aKzBEdx9GLdqoGk562YXXpy-oJ1KzuwI_TrdAoUI7DEVNNd1I8VGLjYywQC4bBsbCPh3poFIyvL5OE/s400/logo1.png" width="400" /></a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Friends, get yourself ready for the <b>29th International Conference on VLSI Design</b> and <b>15th International Conference on Embedded Systems</b> which will be held during <b>January 4-8, 2016 at Kolkata, West Bengal, India</b>.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The theme for the conference this year is <b>"Technologies for a Safe and Inclusive World"</b>. This 5 day conference comprises: first three days (January 4 to 6, 2016) of main conference followed by Tutorials during the last two days (January 7-8, 2016).</div>
<div style="text-align: justify;">
<br /></div>
<div>
<div style="text-align: justify;">
The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Today semiconductor technology is poised to look beyond its traditional bastions of application with pervasive impact on healthcare, environment, energy, transportation, and disaster management. The <b>29th International Conference on VLSI Design</b> and the <b>15th International Conference on Embedded Systems</b> will bring together industry and academia to present front-end technology under the theme of <b>Technologies for a Safe and Inclusive World</b>.</div>
</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<div>
The Technical tracks will be grouped under the theme track and the three broad categories namely, <b>Design Methodologies and Technology</b>, <b>Design Tools and EDA and Embedded System Design and Tools</b>. The conference proceedings will be published by the <b>IEEE Computer Society Press</b>. Selected papers from this conference will also be published as special issues of top archival journals. </div>
<div>
<br /></div>
<div>
Authors are invited to submit full-length (6 pages maximum) in IEEE CS proceedings format, original, unpublished papers with an abstract (200 words maximum) under the tracks listed below. To enable double blind review, the author list should be omitted from the main document. Papers violating length and blind-review criteria would be excluded from the review process. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered for publication. </div>
<div>
<br /></div>
<div>
<b>Track:</b> <b>Design Methodology and Technology </b></div>
<div>
<b>D1: System-level Design</b> </div>
<div>
ESL, System-level design methodology, Multicore systems, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect tolerant architectures </div>
<div>
<br /></div>
<div>
<b>D2: Advances in Digital Design </b></div>
<div>
Logic and Physical synthesis; Place & Route, Clock Tree, Physical Verification, Timing and Signal integrity, Power analysis and integrity, OCV, DFM; DFY; Challenges for advanced technology nodes </div>
<div>
<br /></div>
<div>
<b>D3: Analog / RF Design </b></div>
<div>
Analog Mixed Signal IP; High-Speed interfaces; SDR and wireless; Low-power Analog and RF; Effective use of Spectrum; Memory Design, Standard Cell Design </div>
<div>
<br /></div>
<div>
<b>D4: Power Aware Design </b></div>
<div>
Low-power design, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools </div>
<div>
<br /></div>
<div>
<b>D5: Devices / Circuits </b></div>
<div>
New Devices and architectures; Low power devices; Modeling and Simulation; Multi-domain simulation; Numerical methods; Device/circuit level variability models; Reliability simulation </div>
<div>
<br /></div>
<div>
<b>D6: Emerging Technologies</b> </div>
<div>
Nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Nano-electronics and Nano-circuits, Nano-sensors, MEMS applications, Nano-assemblies and Devices, Non-classical CMOS; Post-CMOS devices; Biomedical circuits, Carbon Nano-tubes based computing </div>
<div>
<br /></div>
<div>
<b>Track : Design Tools and EDA </b></div>
<div>
<b>T1: Design Verification </b></div>
<div>
Functional Verification; Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies </div>
<div>
<br /></div>
<div>
<b>T2: Test Reliability and Fault-Tolerance</b> </div>
<div>
DFT, Fault modelling/simulation; ATPG; Low Power DFT; BIST & Repair; Delay test; Fault tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test; static and dynamic defect- and fault-recoverability, and variation-aware design </div>
<div>
<br /></div>
<div>
<b>T3: Computer-Aided Design (CAD)</b> </div>
<div>
Hardware/software co-design, logic and behavioural synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction) </div>
<div>
<br /></div>
<div>
<b>Track : Embedded System Design and Tools </b></div>
<div>
<b>E1: Embedded Systems </b></div>
<div>
Hardware/Software co-design & verification; Reconfigurable computing; Embedded multi-cores SOC and systems; Embedded software including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip; Embedded applications, Platforms & Case studies </div>
<div>
<br /></div>
<div>
<b>E2: FPGA Design and Reconfigurable Systems </b></div>
<div>
FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping </div>
<div>
<br /></div>
<div>
<b>E3: Wireless Systems </b></div>
<div>
Wireless Sensor Networks, Low Power wireless Systems, Embedded Wireless, Wireless protocols, Wireless Power / Charging </div>
<div>
<br /></div>
<div>
<b>Theme Track : Technologies for a Safe and Inclusive World </b></div>
<div>
<b>H1: Technologies for Healthcare Applications </b></div>
<div>
<b>H2: Technologies for Smart Management of Energy Systems </b></div>
<div>
<b>H3: Technologies for Intelligent and Secure Transportation Systems </b></div>
<div>
<b>H4: Technologies for Safety Assurance of Embedded Circuits and Systems </b></div>
<div>
<b>H5: Technologies for Secure Embedded Circuits and Systems </b></div>
<div>
<br /></div>
<div>
<br /></div>
<div>
Proposals for Tutorials and Special Sessions/Panel Discussion on the above-listed topics (but not limited to) are invited. Please check conference website for details. </div>
<div>
<br /></div>
<div>
Important dates are the following: </div>
<div>
<br /></div>
<div>
<b>REGULAR PAPERS </b></div>
<div>
Abstract submission : July 19, 2015 (Sunday) </div>
<div>
Full Paper submission : July 26, 2015 (Sunday) </div>
<div>
Acceptance Notification : Sep 26, 2015 (Saturday) </div>
<div>
Camera-ready version : Oct 11, 2015 (Sunday) </div>
<div>
<br /></div>
<div>
<b>TUTORIALS</b> </div>
<div>
Tutorial Proposals : July 19, 2015 (Sunday) </div>
<div>
Acceptance Notification : Sep 26, 2015 (Saturday) </div>
<div>
Presentation Slides : Nov 15, 2015 (Sunday) </div>
<div>
<br /></div>
<div>
<b>SPECIAL SESSIONS </b></div>
<div>
Proposal submission : July 19, 2015 (Sunday) </div>
<div>
General Chairs </div>
<div>
Pradip Bose, IBM </div>
<div>
Susmita Sur-Kolay, ISI </div>
<div>
<br /></div>
<div>
Vice-General Chairs </div>
<div>
Indranil Sengupta, IITKGP </div>
<div>
Parthasarathi Dasgupta, IIMC </div>
<div>
<br /></div>
<div>
Program Chairs </div>
<div>
Krishnendu Chakrabarty, Duke </div>
<div>
Pallab Dasgupta, IITKGP </div>
<div>
Partha P. Das, IITKGP </div>
<div>
<br /></div>
<div>
Tutorial Chairs </div>
<div>
Hafizur Rahaman, IIEST </div>
<div>
Prabhat Mishra, UF </div>
<div>
Annajirao Garimella, Intel </div>
<div>
<br /></div>
<div>
Publiciy chairs </div>
<div>
Chandan Giri, IIESTS </div>
<div>
Ken Stevens, U. Utah </div>
<div>
Monica Pereira, UFRN </div>
<div>
Robert Wille, U. Bremen </div>
<div>
Swarup Bhunia, CWRU </div>
<div>
T. -Y. Ho, NCKU</div>
</div>
<div style="text-align: justify;">
<br /></div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0Kolkata, West Bengal, India22.572646 88.36389499999995721.6349985 87.073001499999961 23.5102935 89.654788499999952tag:blogger.com,1999:blog-4978237314452270227.post-39451129262553760872015-09-21T00:02:00.000-07:002015-09-21T00:02:38.849-07:00SVEditor - A SystemVerilog Editor Eclipse Plugin<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj6P5JWm0mKm7-p6jHd0KBCakkjY7xK7fQ1K5oOYZBr2fItyYp2OAMEs8Mrs6IK_c_puYf8HRpc65xM1TMu6P8ZH7g4B_VeSk27b0gAgsmzH_FFxiMYZLHGrtPOvqLxjlBHcOk7ToYUqq23/s1600/window_img_128_128.gif" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"><img border="0" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj6P5JWm0mKm7-p6jHd0KBCakkjY7xK7fQ1K5oOYZBr2fItyYp2OAMEs8Mrs6IK_c_puYf8HRpc65xM1TMu6P8ZH7g4B_VeSk27b0gAgsmzH_FFxiMYZLHGrtPOvqLxjlBHcOk7ToYUqq23/s200/window_img_128_128.gif" width="200" /></a></div>
<div style="text-align: justify;">
Source code editors have features specifically designed to simplify and speed up input of source code, such as syntax highlighting, indentation, autocomplete and bracket matching functionality. Variety of source code editors are available for VLDH, Verilog & SystemVerilog. We have already posted feb of them like Scriptum, and Emacs. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
You might be interested in : </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<a href="http://www.vlsiencyclopedia.com/2011/06/scriptum-free-vhdl-and-verilog-text.html">Scriptum - Free VHDL and Verilog Text Editor</a> </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<a href="http://www.vlsiencyclopedia.com/2011/06/gnu-emacs-customizable-text-editor.html">GNU Emacs - A Customizable Text Editor</a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<a href="http://sveditor.sourceforge.net/">SVEditor</a> is an Eclipse-based IDE (integrated development environment) for <a href="http://www.vlsiencyclopedia.com/p/systemverilog.html">SystemVerilog</a> and Verilog development. It provides a colourising editor for SystemVerilog with support for source navigation, content assist, source indent and auto-indent, SystemVerilog source templates and context-sensitive viewing of source documentation. Users have praised SVEditor for some of its features, such as searching for a colourisation of SystemVerilog keywords or words in a directory, auto-completion and some content assist. We believe that you can use SVEditor for debugging if you love <a href="http://www.vlsiencyclopedia.com/2011/06/gnu-emacs-customizable-text-editor.html">emacs</a>. Quoting from sourceforge.net, one user has said, “I’m totally stoked that this project is under active development. The tool is already very useful.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>SVEditor</b> provides a variety of features to make developing designs and testbench environments in SystemVerilog simpler and more efficient.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Features at a glance</b></div>
<div style="text-align: justify;">
The application uses a scanner that is similar to ctags for extracting the information from SystemVerilog and Verilog source files. It is engineered to be tolerant of errors, as well as to ignore unrecognized language constructs.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Among some of SVEditor’s features, we can mention colorizing for SystemVerilog keywords, outline view linked with editor, file structure view, SystemVerilog source index, syntax coloring editor, content assist, and cross-linking between data structure usage and declaration.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
There are multiple ways to install the <b>SVEditor</b> software on your GNU/Linux computer, considering the fact that we’ve already installed the latest <b>JRE (Java Runtime Environment)</b> and <b>Eclipse IDE</b> software.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
For exemple, you can download the latest version of the project as a JAR archive that can be opened into an existing Eclipse environment, you can search the application in the main software repositories of your GNU/Linux distribution, or compile it yourself using the source package provided right here on Softpedia.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
For more details, do not hesitate to check out the project’s <a href="http://sveditor.sourceforge.net/" target="_blank">website</a>.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Supported operating systems:</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Taking a look under the hood of the <b>SVEditor</b> application, we can notice that it has been written entirely in the Java programming language and integrates with the <b>Eclipse IDE</b> for its graphical user interface.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
If you don't have Eclipse IDE installed then here is link to download page of Eclipse IDE. <a href="https://eclipse.org/downloads/" target="_blank">Download Eclipse IDE</a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Being written in <b>Java</b>, SVEditor is a cross-platform software that runs on all operating ssytems where the <b>Java Runtime Environment</b> and Eclipse IDE are available, including <b>GNU/Linux, Microsoft Windows and Mac OS X</b>. It has been successfully tested on computers supporting either of the <b>64-bit (x86_64) or 32-bit (x86) CPU architectures</b>.</div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-40947372241689476752015-09-11T00:22:00.001-07:002020-08-14T02:12:19.460-07:00UVM Interview Questions - 4<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<b>Q26: What is p_sequencer ? OR Difference between m_sequencer and p_sequencer?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
m_sequencer is the default handle for uvm_vitual_sequencer and p_sequencer is the hook up for child sequencer.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>m_sequencer</b> is the generic uvm_sequencer pointer. It will always exist for the uvm_sequence and is initialized when the sequence is started.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>p_sequencer</b> is a typed-specific sequencer pointer, created by registering the sequence to the sequencer using macros (`uvm_declare_p_sequencer) . Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, etc.). p_sequencer will not exist if we have not registered the sequence with the `uvm_declare_p_sequencer macros.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The drawback of p_sequencer is that once the p_sequencer is defined, one cannot run the sequence on any other sequencer type.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q27: What is the difference between Active mode and Passive mode with respect to agent?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
An agent is a collection of a sequencer, a driver and a monitor.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
In <b>active mode</b>, the sequencer and the driver are constructed and stimulus is generated by sequences sending sequence items to the driver through the sequencer. At the same time the monitor assembles pin level activity into analysis transactions.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
In <b>passive mode</b>, only the monitor is constructed and it performs the same function as in an active agent. Therefore, your passive agent has no need for a sequencer. You can set up the monitor using a configuration object.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q28: What is the difference between copy and clone?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The built-in <b>copy()</b> method executes the __m_uvm_field_automation() method with the required copy code as defined by the field macros (if used) and then calls the built-in <b>do_copy() </b>virtual function. The built-in do_copy() virtual function, as defined in the uvm_object base class, is also an empty method, so if field macros are used to define the fields of the transaction, the built-in copy() method will be populated with the proper code to copy the transaction fields from the field macro definitions and then it will execute the empty do_copy() method, which will perform no additional activity.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The <b>copy()</b> method can be used as needed in the UVM testbench. One common place where the copy() method is used is to copy the sampled transaction and pass it into a sb_calc_exp() (scoreboard calculate expected) external function that is frequently used by the scoreboard predictor.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The <b>clone()</b> method calls the create() method (constructs an object of the same type) and then calls the copy() method. It is a one-step command to create and copy an existing object to a new object handle.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q29: What is UVM factory? </b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
UCM Factory is used to manufacture (create) UVM objects and components. Apart from creating the UVM objects and components the factory concept essentially means that you can modify or substitute the nature of the components created by the factory without making changes to the testbench. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
For example, if you have written two driver classes, and the environment uses only one of them. By registering both the drivers with the factory, you can ask the factory to substitute the existing driver in environment with the other type. The code needed to achieve this is minimal, and can be written in the test.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q30: What are the types of sequencer? Explain each?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
There are two types of sequencers :</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>uvm_sequencer #(REQ, RSP) :</b></div>
<div style="text-align: justify;">
When the driver initiates new requests for sequences, the sequencer selects a sequence from a list of available sequences to produce and deliver the next item to execute. In order to do this, this type of sequencer is usually connected to a driver uvm_driver #(REQ, RSP).</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>uvm_push_sequencer #(REQ, RSP) :</b></div>
<div style="text-align: justify;">
The sequencer pushes new sequence items to the driver, but the driver has the ability to block the item flow when its not ready to accept any new transactions. This type of sequencer is connected to a driver of type uvm_push_driver #(REQ, RSP).</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b><span style="font-size: x-large;"><a href="http://www.vlsiencyclopedia.com/2015/09/uvm-interview-questions-3.html"><< PREVIOUS</a> <a href="http://www.vlsiencyclopedia.com/2015/11/uvm-interview-questions-5.html" rel="nofollow">NEXT >></a></span></b></div>
<div style="text-align: justify;">
<br /></div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-61826754764119577862015-09-10T21:50:00.001-07:002020-08-14T02:06:42.222-07:00UVM Interview Questions - 3<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<b>Q21: What is analysis port?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method write implemented in another component, specifically a subscriber.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
port, export, and imp classes used for transaction analysis.</div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
<b>uvm_analysis_port</b></div>
<div style="text-align: justify;">
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.</div>
<div style="text-align: justify;">
<b>uvm_analysis_imp</b></div>
<div style="text-align: justify;">
Receives all transactions broadcasted by a uvm_analysis_port.</div>
<div style="text-align: justify;">
<b>uvm_analysis_export</b></div>
<div style="text-align: justify;">
Exports a lower-level uvm_analysis_imp to its parent.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q22: What is TLM FIFO?</b></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
In simpler words TLM FIFO is a FIFO between two UVM components, preferably between Monitor and Scoreboard. Monitor keep on sending the DATA, which will be stored in TLM FIFO, and Scoreboard can get data from TLM FIFO whenever needed.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
// Create a FIFO with depth 4</div>
<div style="text-align: justify;">
tlm_fifo = new ("uvm_tlm_fifo", this, 4);</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q23: How sequence starts?</b></div>
<div style="text-align: justify;">
start_item starts the sequence</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
virtual task start_item (<span class="Apple-tab-span" style="white-space: pre;"> </span>uvm_sequence_item <span class="Apple-tab-span" style="white-space: pre;"> </span>item, <span class="Apple-tab-span" style="white-space: pre;"> </span></div>
<div style="text-align: justify;">
int set_priority<span class="Apple-tab-span" style="white-space: pre;"> </span> = -1,</div>
<div style="text-align: justify;">
uvm_sequencer_base sequencer<span class="Apple-tab-span" style="white-space: pre;"> </span> = null<span class="Apple-tab-span" style="white-space: pre;"> </span>)</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
start_item and finish_item together will initiate operation of a sequence item. If the item has not already been initialized using create_item, then it will be initialized here to use the default sequencer specified by m_sequencer. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q24: What is the difference between UVM RAL model backdoor write/read and front door write/read ?</b></div><div style="text-align: justify;"><b><br /></b></div>
<div style="text-align: justify;">
Fontdoor access means using the standard access mechanism external to the DUT to read or write to a register. This usually involves sequences of time-consuming transactions on a bus interface. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Backdoor access means accessing a register directly via hierarchical reference or outside the language via the PLI. A backdoor reference usually in 0 simulation time.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q25: What is objection?</b></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
The objection mechanism in UVM is to allow hierarchical status communication among components which is helpful in deciding the end of test.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
There is a built-in objection for each in-built phase, which provides a way for components and objects to synchronize their testing activity and indicate when it is safe to end the phase and, ultimately, the test end.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The component or sequence will raise a phase objection at the beginning of an activity that must be completed before the phase stops, so the objection will be dropped at the end of that activity. Once all of the raised objections are dropped, the phase terminates.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Raising an objection: phase.raise_objection(this);</div>
<div style="text-align: justify;">
Dropping an objection: phase.drop_objection(this);<br />
<br />
<b><span style="font-size: x-large;"><a href="http://www.vlsiencyclopedia.com/2015/09/uvm-interview-questions-2.html"><< PREVIOUS</a></span></b> <b style="text-align: left;"><span style="font-size: x-large;"> </span></b><span style="text-align: left;"> </span><span style="font-size: x-large; text-align: left;"> <b><span style="color: blue;"><a href="http://www.vlsiencyclopedia.com/2015/09/uvm-interview-questions-4.html">NEXT >></a></span></b></span></div>
<div style="text-align: justify;">
<br /></div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0tag:blogger.com,1999:blog-4978237314452270227.post-41409403301327764732015-09-09T22:51:00.000-07:002016-12-17T22:11:42.458-08:00UVM Interview Questions - 1<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<b>Q11: Difference between module & class based TB?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Ans:</b> A module is a static object present always during of the simulation.</div>
<div style="text-align: justify;">
A Class is a dynamic object because they can come and go during the life time of simulation.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q12: What is uvm_config_db ? What is difference between uvm_config_db & uvm_resource_db?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Ans:</b> uvm_config_db is a parameterized class used for configuration of different type of parameter into the uvm database, So that it can be used by any component in the lower level of hierarchy.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
uvm_config_db is a convenience layer built on top of uvm_resource_db, but that convenience is very important. In particular, uvm_resource_db uses a "last write wins" approach. The uvm_config_db, on the other hand, looks at where things are in the hierarchy up through end_of_elaboration, so "parent wins." Once you start start_of_simulation, the config_db becomes "last write wins."</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator</div>
<div style="text-align: justify;">
It is extended from the uvm_resource_db#(T), so it is child class of uvm_resource_db#(T)</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q13: What is the advantage and difference of `uvm_component_utils() and `uvm_object_utils()?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Ans:</b> The utils macros define the infrastructure needed to enable the object/component for correct factory operation. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The reason there are two macros is because the factory design pattern fixes the number of arguments that a constructor can have. Classes derived from uvm_object have constructors with one argument, a string name. Classes derived from uvm_component have two arguments, a name and a uvm_component parent. </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The two `uvm_*utils macros inserts code that gives you a factory create() method that delegates calls to the constructors of uvm_object or uvm_component. You need to use the respective macro so that the correct constructor arguments get passed through. This means that you cannot add extra constructor arguments when you extend these classes in order to be able to use the UVM factory.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q14: Difference between `uvm_do and `uvm_rand_send ?</b></div>
<div style="text-align: justify;">
<b><br /></b></div>
<div style="text-align: justify;">
<b>Ans: </b>`uvm_do perform the below steps:</div>
<div style="text-align: justify;">
</div>
<ol>
<li>create</li>
<li>start_item</li>
<li>randomize</li>
<li>finish_item</li>
<li>get_response (optional)</li>
</ol>
<br />
<div style="text-align: justify;">
while `uvm_rand_send perform all the above steps except create. User needs to create sequence / sequence_item.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Q15: Difference between uvm_transaction and uvm_seq_item?</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Ans:</b> <i>class uvm_sequence_item extends uvm_transaction</i></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
uvm_sequence_item extended from uvm_transaction only, uvm_sequence_item class has more functionality to support sequence & sequencer features. uvm_sequence_item provides the hooks for sequencer and sequence , So you can generate transaction by using sequence and sequencer , and uvm_transaction provide only basic methods like do_print and do_record etc .</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-size: x-large;"><a href="http://www.vlsiencyclopedia.com/2015/09/uvm-interview-questions.html"><b><< PREVIOUS</b></a> <a href="http://www.vlsiencyclopedia.com/2015/09/uvm-interview-questions-2.html"><b>NEXT >></b></a></span></div>
<div style="text-align: justify;">
<br /></div>
</div>
VLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.com0