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Thursday 22 January 2015

SystemVerilog Built-In Data Types

Verilog-1995 has two basic data types: variables (reg) and nets, that hold four-state values: 0, 1, Z, and X. RTL code uses variables to store combinational and sequential values. Variables can be unsigned single or multi-bit (reg [7:0] m), signed 32-bit variables (integer), unsigned 64-bit variables (time), and floating point numbers (real). Variables can be grouped together into arrays that have a fixed size. All storage is static, meaning that all variables are alive for the entire simulation and routines cannot use a stack to hold arguments and local values. A net is used to connect parts of a design such as gate primitives and module instances. Nets come in many flavors, but most designers use scalar and vector wires to connect together the ports of design blocks.

SystemVerilog adds many new data types to help both hardware designers and verification engineers.

The logic type

The one thing in Verilog that always leaves new users scratching their heads is the difference between a reg and a wire. When driving a port, which should you use? How about when you are connecting blocks? System-Verilog improves the classic reg data type so that it can be driven by continuous assignmentsgates and modules, in addition to being a variable. It is given the new name logic so that it does not look like a register declaration. The one limitation is that a logic variable cannot be driven by multiple drivers such as when you are modeling a bidirectional bus. In this case, the variable needs to be a net-type such as wire.

Example: shows the SystemVerilog logic type.
module logic_data_type(input logic rst_h);
  parameter CYCLE = 20;
  logic q, q_l, d, clk, rst_l;

initial begin
  clk <= 0; // Procedural assignment
  forever #(CYCLE/2) clk = ~clk;

assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module


Two-state types

SystemVerilog introduces several two-state data types to improve simulator performance and reduce memory usage, over four-state types. The simplest type is the bit, which is always unsigned. There are four signed types: byte, shortint, int, and longint.

shortint i                // 2-state, 16-bit signed
int i                        // 2-state, 32-bit signed
longint i                 // 2-state, 64-bit signed
byte b                    // 2-state, 8-bit signed
bit b;                      // 2-state, single-bit
bit [31:0] b32;       // 2-state, 32-bit unsigned

You might be tempted to use types such as byte to replace more verbose declarations such as logic [7:0]. Hardware designers should be careful as these new types are signed variables, so a byte variable can only count up to 127, not Chapter 2: Data Types 29 the 255 you may expect. (It has the range -128 to +127.) You could use byte unsigned, but that is more verbose than just bit [7:0]. Signed variables may cause unexpected results with randomization, as discussed in Chapter 6. Be careful connecting two-state variables to the design under test, especially its outputs. If the hardware tries to drive an X or Z, these values are converted to a two-state value, and your testbench code may never know. Don’t try to remember if they are converted to 0 or 1; instead, always check for propagation of unknown values. Use the $isunknown operator that returns 1 if any bit of the expression is X or Z.

Example: Checking for four-state values

if ($isunknown(iport)
$display("@%0d: 4-state value detected on input port",
$time, iport);

Next : SystemVerilog Enumerated Types

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