The keyword INERTIAL may be used in the signal assignment statement to specify an inertial delay, or it may be left out because inertial delay is used by default in VHDL signal assignment statements which contain “after” clauses.
If the optional REJECT construct is not used, the specified delay is then used as both the ‘inertia’ (i.e. minimum input pulse width requirement) and the propagation delay for the signal. Note that in the example above, pulses on Input narrower than 10ns are not observed on Output.
Featured post
Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
Saturday, 13 October 2012
VHDL-Inertial Delay
Subscribe to:
Post Comments (Atom)
-
Q31: What is virtual sequencer and virtual sequence in UVM? A virtual sequencer is a sequencer that is not connected to a driver itsel...
-
In Verilog certain type of assignments or expression are scheduled for execution at the same time and order of their execution is not guara...
-
In previous post of this SystemVerilog Tutorial we talked about enumerated type in detail. Now we will look at the constants in SystemVe...
-
This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage. ...
-
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
No comments:
Post a Comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.