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Friday 3 August 2012

SystemVerilog Interview Questions

1. What is clocking block?
2. What are modports?
3. What are interfaces?
4. What are virtual interfaces? How can it be used?
5. What is a class?
6. What is program block?
7. What is a mailbox?
8. What are semaphores?
9. Why is reactive scheduler used?
10. What are rand and randc?
11. What is the difference between keywords: rand and randc?
12. What is the use of always_ff?
13. What are static and automatic functions?
14. What is the procedure to assign elements in an array in systemverilog?
15. What are the types of arrays in systemverilog?
16. What are assertions?
17. What is the syntax for ## delay in assertion sequences?
18. What are virtual classes?
19. Why are assertions used?
20. Explain the difference between data type?s logic and reg and wire.
21. What is callback?
22. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
23. Explain event regions in systemverilog?
24. What are the types of coverages available in systemverilog?
25. How can you detect a deadlock condition in FSM?
26. What is mutex?
27. What is the significance of seed in randomization?
28. What is the difference between code coverage and functional coverage?
29. If the functional coverage is more that code coverage, what does it means?
30. How we can have #delay which is independent of time scale in system verilog?
31. What are constraints in systemverilog?
32. What are the different types of constraints in systemverilog?
33. What is an if-else constraint?
34. What is inheritance and give the basic syntax for it?
35. What is the difference between program block and module?
36. What is final block?
37. What are dynamic and associative arrays?
38. What is an abstract class?
39. What is the difference between $random and $urandom?
40. What is the use of $cast?
41. What is the difference between mailbox and queue?
42. What are bidirectional constraints?
43. What is circular dependency and how to avoid this problem?
44. What is the significance of super keyword?
45. What is the significance of this keyword?
46. What are input and output skews in clocking block?
47. What is a scoreboard?
48. Mention the purpose of dividing time slots in systemverilog?
49. What is static variable?
50. In simulation environment under what condition the simulation should end?
51. What is public declaration?
52. What is the use of local?
53. Difference b/w logic & bit.
54. How to take an asynchronous signal from clocking block?
55. What is fork-join, types and differences?
56. Difference between final and initial blocks?
57. What are the different layers in Testbench?
58. What is the use of modports?
59. What is the use of package?
60. What is the difference between bit [7:0] and byte?
61. What is chandle in systemverilog ?
62. What are the features added in systemverilog for function and task?
63. What is DPI in systemverilog?
64. What is inheritance?
65. What is polymorphism?
66. What is Encapsulation?
67. How to count number of elements in mailbox?
68. What is covergroup?
69. What are super, abstract and concrete classes?
70. Explain some coding guidelines you followed in your environment ?
71. What is Verification plan? What it contains?
72. Explain how messages are handled?
73. What is difference between define and parameter?
74. Why ?always? block not allowed inside program block?
75. How too implement clock in program block?
76. How to kill process in fork/join ?
77. Difference between Associative and dynamic arrays?
78. How to check whether randomization is successful or not?
79. What is property in SVA?
80. What advantages of Assertions?
81. What are immediate Assertions?
82. What are Assertion severity system level task? What happens if we won?t specify these tasks?
83. What is difference between Concurrent and Immediate assertions?
84. In which event region concurrent assertions will be evaluated?
85. What are the main components in Concurrent Assertions?
86. What is Consecutive Repetition Operator in SVA?
87. What is goto Replication operator in SVA?
88. What is difference between x [->4:7] and x [=4:7] in SVA?
89. What are implication operators in Assertions?
90. Can a constructor qualified as protected or local in systemverilog?
91. What are advantages of Interfaces?
92. How automatic variables are useful in Threads?

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  1. Thanks, I was waiting for this post. :)
    Nice collection of SystemVerilog Interview Questions


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