Featured post

Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Wednesday, 12 December 2012

SystemVerilog Virtual Interfaces

This is most common SystemVerilog interview question that is asked while you will appearing for the position of Verification Engineer.

As you know an interface encapsulate a group of inter-related wires, along with their directions (via mod-ports) , synchronization details (via clocking block) , functions and tasks.

The major usage of interface is to simplify the connection between modules.
But Interface can’t be instantiated inside program block, class (or similar non-module entity in System Verilog).

But we needed to be driven from verification environment like class.

To solve this issue virtual interface concept was introduced in System Verilog. A virtual interface is just a pointer to a physical interface. i.e. Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an interface (that implies the class can drive the interface using the virtual interface).

Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design. A virtual interface allows the same subprogram to operate on different portions of a design and to dynamically control the set of signals associated with the subprogram. Instead of referring to the actual set of signals directly, users are able to manipulate a set of virtual signals. 

interface sample_if() ;  // SystemVerilog Interface
  logic a ;
  logic b ;
  modport TB(input a, output b) ; // Modport declaration 
endinterface

class Driver ;
  virtual sample_if inf ;           // Virtual Interface declaration in class
  function new (sample_if inf)
    this.inf = inf ;
  endfunction
  task main () ;
  inf.a =a ;
endtask
endclass

2 comments:

  1. Could you please tell me why Interface can’t be instantiated inside program block, class (or similar non-module entity in System Verilog) ?

    ReplyDelete
    Replies
    1. A class is a dynamic property, which is created at run time while an interface is a static property, which is created at compile time. So, it is not possible to instantiate a physical interface inside a class. But, a handle of virtual interface is used to reference a physical interface.

      Delete

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.