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Wednesday 11 July 2012

Key Features of upcoming DDR4 memory

Can you believe DDR3 has been present in home PC systems for three years already? It still has another two years as king of the hill before DDR4 will be introduced, and the industry currently isn’t expecting volume shipments of DDR4 until 2013.

JEDEC isn’t due to confirm the DDR4 standard until next year, but following on from the MemCon Tokyo 2010, Japanese website PC Watch has combined the roadmaps of several memory companies on what they expect DDR4 to offer.

Following are the new features proposed for DDR4:

  • Three data width offerings: x4, x8 and x16
  • New JEDEC POD12 interface standard for DDR4 (1.2V)
  • Differential signaling for the clock and strobes
  • New termination scheme versus prior DDR versions: In DDR4, the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.
  • Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
  • Burst length of 8 and burst chop of 4
  • Data masking
  • DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
  • New CRC for data bus: Enabling error detection capability for data transfers – especially beneficial during write operations and in non-ECC memory applications.
  • New CA parity for command/address bus: Providing a low-cost method of verifying the integrity of command and address transfers over a link, for all operations.
  • DLL off mode supported

It looks like we should expect frequencies introduced at 2,133MHz and it will scale to over 4.2GHz with DDR4. 1,600MHz (10ns) could still well be the base spec for sever DIMMs that require reliability, but it’s expected that JEDEC will create new standard DDR3 frequency specifications all the way up to 2,133MHz, which is where DDR4 should jump off.

As the prefetch per clock should extend to 16 bits (up from 8 bits in DDR3), this means the internal cell frequency only has to scale the same as DDR2 and DDR3 in order to achieve the 4+GHz target.

The downside of frequency scaling is that voltage isn’t dropping fast enough and the power consumption is increasing relative to PC-133. DDR4 at 4.2GHz and 1.2V actually uses 4x the power of SDRAM at 133MHz at 3.3V. 1.1V and 1.05V are currently being discussed, which brings the power down to just over 3x, but it depends on the quality of future manufacturing nodes – an unknown factor.

While 4.2GHz at 1.2V might require 4x the power it’s also a 2.75x drop in voltage for a 32 fold increase in frequency: that seems like a very worthy trade off to us – put that against the evolution of power use in graphics cards for a comparison and it looks very favorable.


One area where this design might cause problems is enterprise computing. If you’re using a lot of DIMMs, considerably higher power, higher heat and higher cost aren’t exactly attractive. It’s unlikely that DDR4 4.2GHz will reach a server rack near you though: remember most servers today are only using 1,066MHz DDR3 whereas enthusiast PC memory now exceeds twice that.

Server technology will be slightly different and use high performance digital switches to add additional DIMM slots per channel (much like PCI-Express switches we expect, but with some form of error prevention), and we expect it to be used with the latest buffered LR-DIMM technology as well, although the underlying DDR4 topology will remain the same.

This is the same process the PCI bus went through in its transition to PCI-Express: replacing anything parallel nature with a serial approach. DDR4 will become a point-to-point bus and the parallelism is being left with the memory controller itself with multiple memory channels.

If we look at Intel’s upcoming LGA2011 socket that is anticipated to use a quad-channel memory interface and a single DIMM per channel, it’s now quite obvious that future CPUs using this socket stand a good chance of using DDR4, especially as LGA1366 has had a well defined three year lifespan. In the same timeframe DDR4 could see considerable market acceptance so it’s a smart move by Intel.

The big questions remain to be answered then: is it a consumer (cost) friendly process and how well does TSV cope with overclocking? We’ll have to wait for the first samples in 2011-2012 to find out.

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