SystemVerilog Constants

In previous post of this SystemVerilog Tutorial we talked about enumerated type in detail. Now we will look at the constants in SystemVerilog. There are several types of constants in systemVerilog. The classic Verilog way to create a constant is with a text macro. 

On the plus side, macros have global scope and can be used for bit field definitions and type definitions.
On the negative side, macros are global, so they can cause conflicts if you just need a local constant. 
Lastly, a macro requires the ` character so that it will be recognized and expanded.

In SystemVerilog, parameters can be declared at the $root level so they can be global. This approach can replace many Verilog macros that were just being used as constants. You can use a typedef to replace those large macros. The next choice is a parameter. A Verilog parameter was loosely typed and was limited in scope to a single module. Verilog-2001 added typed parameters, but the limited scope kept parameters from being widely used.

SystemVerilog allows you to declare constant identifiers. You can declare an identifier as constant by prefixing the usual identifier definition with the keyword const. At the time of defining a constant, the user needs to provide a value for the identifier. At any later stage in the code, a SystemVerilog compiler disallows any modification to the value bound to the identifier.


// Constant bit 
const bit [63:0] data_bus='hB6AB31E0;
// Constant int bus width
const int bus_width = 8;
// Constant String VLSI Encyclopedia
const string name = "VLSI Encyclopedia";
// Constant method
function int count (const ref bytes[]);

In addition to a normal identifier declaration, the const modifier can be used to declare function/task arguments as constants. An argument to a function may be of either a pass-by-value or pass-by-reference type. When using pass-by-value semantics, the const modifier has the usual meaning; the locally bound parameter's value can not be changed in the given function.

When using pass-by-reference semantic (as is the case with const ref arrays), the SV compiler ensures that the referenced value is not modified by the code in the function. Normally arrays (even dynamic ones) are passed by value. 

Since arrays could be very big, SystemVerilog allows you to declare an array parameter type as a reference, by prefixing the function parameter with keyword ref. But this introduces the danger of a user inadvertently altering the arrays (actually it's elements) value. By prefix const to the reference array parameter, you can avoid this danger. The compiler would ensure that inside the function, a user can not alter the arrays value.

Note :
Constant identifiers in SystemVerilog are not compile time constants. As a result it is not allowed to use a constant as a range parameter for an array. This is much unlike C++, wherein constants are compile time constants. As an alternative, SystemVerilog users are allowed to use parameters (aka parameterized functions and classes) as range specifiers for an array.

Previous : SystemVerilog Enumerated Types
Next : SystemVerilog Strings

No comments:

Post a Comment

Please provide valuable comments and suggestions for our motivation...

Popular Posts