library ieee;
use ieee.std_logic_1164.all;
entity my_and is
port (a, b : in std_logic;
c : out std_logic);
end my_and;
architecture my_and_arc of my_and is
begin
c <= a and b;
end my_and_arc;
As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...
library ieee;
use ieee.std_logic_1164.all;
entity my_and is
port (a, b : in std_logic;
c : out std_logic);
end my_and;
architecture my_and_arc of my_and is
begin
c <= a and b;
end my_and_arc;
No comments:
Post a comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.