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Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Thursday, 27 February 2014

Assertion Debugging in Questa – few tips

Playing around debugging some complex assertions in Qeusta? Here are some tips:

1. Use vsim –assertdebug

2. Add –novopt for trivial code containing assertions + stim alone as otherwise many signals get optimized away. On real designs, perhaps you are better off with +acc* (Read doc for more)

3. Once the GUI comes up, the assertions are not listed in its own browser – ideally I would have liked to see a menu item under “Tools” menu. But it is hidden under “View –> Coverage –> Assertions” – GOK why! (GOK – God Only Knows)  :)

4. Before starting simulation, enable ATV

5. After sim one can do “view ATV” for advanced debug!



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