Featured post

Top 5 books to refer for a VHDL beginner

VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Thursday 27 February 2014

Assertion Debugging in Questa – few tips

Playing around debugging some complex assertions in Qeusta? Here are some tips:

1. Use vsim –assertdebug

2. Add –novopt for trivial code containing assertions + stim alone as otherwise many signals get optimized away. On real designs, perhaps you are better off with +acc* (Read doc for more)

3. Once the GUI comes up, the assertions are not listed in its own browser – ideally I would have liked to see a menu item under “Tools” menu. But it is hidden under “View –> Coverage –> Assertions” – GOK why! (GOK – God Only Knows)  :)

4. Before starting simulation, enable ATV

5. After sim one can do “view ATV” for advanced debug!



Get free daily email updates!

Follow us!

No comments:

Post a Comment

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.