Most modern EDA tools will accept both VHDL and Verilog, and even combination of the two in the same design. Even though engineers try to convert from VHDL to Verilog, or Verilog to VHDL in some cases depends on their requirement in design work flow.
Possible Reasons of Code Conversion Between VHDL and Verilog
- To reuse existing designs
- To maintain both version of a design. Verilog for commercial, industrial purposes and VHDL for DoD requirements.
- To design, support the code for different countries like US, Europe and or Asia where preference for particular language differs.
As a general rule, it is better to write own coding in the targeted HDL such as VHDL or Verilog. However, the time you will spend on the “manual translation” could also be used to make a design on your own.
The commercially available code conversion/translation tools convert the code as module wise, and may not necessarily support every possible construct you can find in VHDL or Verilog.
In case of urgent need, the tools will help in translating the larger code from VHDL to Verilog (and Verilog to VHDL too) on the fly. Few of them are for command line use in UNIX environment, and a few are GUI enabled so that you can execute them in Windows.
VHDL to Verilog (Verilog to VHDL) Code Conversion Translation Tools
Here is the list of some popular Vendors, supply HDL code conversion tools. Few are free download, and others cost a little but gives a demo version with some limitation on code size.
- Synapticad’s V2V Translation Tool, supports both VHDL to Verilog and vice versa
- MyHDL, supports both VHDL to Verilog and vice versa
- TauDelta’s Verilog to VHDL RTL converter
- Trilent Networks HDL Translator
- Alternate System Concepts Inc.
- Avanti Corp.
- Aldec Corporation’s Active-HDL
- X-Tek Corporation’s XHDL
- FTL Systems
- Ocean Logic
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