A day before there was a discussion about Synchronous and Asynchronous reset and Reset Synchronizer. I would like to share my views and some Ideas that I came to know.
Implementation of Synchronous and Asynchronous reset should depend on what you are looking at. There is a timing constraint on the rising edge of the reset ( assuming an active low reset) which can create one cycle uncertainty in the data being latched in by the FF. So for example if the start of a state machine depends on when the input FF gets the data and it doesn't matter if it starts one cycle early or late, there is no problem in using Asynchronous Reset. But if you have a high speed interface with say 6 bits of data being latched by the FF's and reset release happens very close to the clock edge then you have a serious problem that some Flops can get the data and some won't.
So it is really depended on what your design does on what kind of reset you should have. The safe methodology from my point of view is to use Asynch resets as long as the clock starts after the reset has been released. Or to synchronize the Reset with the clock and make sure that the reset network delay including the CLK->Q delay of the synchronizing flop is less then the clock period - the worst removal timing of the FF's on the network.