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VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...

Saturday 3 April 2010

What is Clock Skew?

Given two sequentially-adjacent registers, Ri and Rj, and an equipotential clock distribution network, the clock skew between these two registers is defined as

Tskew-i,j = Tci - Tcj

where Tci and Tcj are the clock delays from the clock source to the registers Ri and Rj, respectively.

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