tag:blogger.com,1999:blog-4978237314452270227.post1638137804488764501..comments2023-07-23T08:50:28.792-07:00Comments on Very Large Scale Integration (VLSI): Myths of Verilog Case StatementVLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.comBlogger3125tag:blogger.com,1999:blog-4978237314452270227.post-53816621080249413192013-09-18T06:47:33.964-07:002013-09-18T06:47:33.964-07:00As Vijay correctly pointed out that the synthesis ...As Vijay correctly pointed out that the synthesis will give input as mux_in[3]<br />instead of mux_in[2], then dosen't this contradict your premise that the casex and casez statements will give the same result(netlist) on synthesis? Please elaborate.Thanks a lot Adityahttps://www.blogger.com/profile/13625022312374535028noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-58089004618146985572013-01-16T19:06:42.860-08:002013-01-16T19:06:42.860-08:00Thanks Vijay for going through this article.
You a...Thanks Vijay for going through this article.<br />You are correct. there is a typo in the schematic. As you synthesised is correct, mux_in[3] will get inferred.<br /><br />Thanks a ton.<br /><br />-- VLSI Encyclopedia TeamVLSI Encyclopediahttps://www.blogger.com/profile/16627288764130002695noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-57052424223687849582013-01-16T00:00:22.379-08:002013-01-16T00:00:22.379-08:00"Now let the case item 3 be changed to 1x.&qu..."Now let the case item 3 be changed to 1x."<br /><br />In the casez synthesis example, is the schematic correct in mux_in[2] being input of one of the muxes?<br /><br />I synthesised in DC and the input is inferred to be mux_in[3].<br />vijaynoreply@blogger.com