UVM Guide for Beginners
Due to increasing trend of UVM for verification, we have created a guide that will assist a novice in building a verification environment using this methodology. We will not focus on verification techniques nor in the best practices in verifying a digital design, this guide was thought in helping you to understand the UVM API and in helping you to successfully compile a complete environment.
The simulator used is Mentor's Questasim but the testbench should compile in any HDL simulator that supports SystemVerilog.
Hi..
ReplyDeleteIs this section incomplete? Talks of chapters 5 onwards, but there are no links?
Hi..
ReplyDeletewhat is the difference between config_db and resourse_db ?
Hi Ram,
DeletePlease refer question #12 in below link
http://www.vlsiencyclopedia.com/2015/09/uvm-interview-questions-1.html