tag:blogger.com,1999:blog-4978237314452270227.post7612663580087895529..comments2023-07-23T08:50:28.792-07:00Comments on Very Large Scale Integration (VLSI): SystemVerilog Fixed ArraysVLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.comBlogger1125tag:blogger.com,1999:blog-4978237314452270227.post-38597144807235097692019-02-24T06:22:37.559-08:002019-02-24T06:22:37.559-08:00Hi ,
I have a doubt regarding initialization of Mu...Hi ,<br />I have a doubt regarding initialization of Multi Dimensional Arrays in system verilog ,<br />do we support for logic a[7:0] = '{{0,1,2}:'1,default:'0}; kind of support in system verilogRama Krishnahttps://www.blogger.com/profile/17607422326619307548noreply@blogger.com