tag:blogger.com,1999:blog-4978237314452270227.post3574628891793166211..comments2023-07-23T08:50:28.792-07:00Comments on Very Large Scale Integration (VLSI): Finite State Machine (FSM) Coding In VHDLVLSI Encyclopediahttp://www.blogger.com/profile/16627288764130002695noreply@blogger.comBlogger18125tag:blogger.com,1999:blog-4978237314452270227.post-81177352038923755782015-08-06T04:04:04.706-07:002015-08-06T04:04:04.706-07:00Please refer below guide for Quartus!!
https://goo...Please refer below guide for Quartus!!<br />https://goo.gl/FGO8Ow<br /><br />Thanks,<br />Team VLSI EncyclopediaVLSI Encyclopediahttps://www.blogger.com/profile/16627288764130002695noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-64664686962830606042015-08-02T20:22:34.985-07:002015-08-02T20:22:34.985-07:00How can I run this code in Quartus II?How can I run this code in Quartus II?Pencari Ilmuhttps://www.blogger.com/profile/09402469676732263494noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-28892069907684876632015-03-02T20:47:42.933-08:002015-03-02T20:47:42.933-08:00Yes you are right... the melay implementation will...Yes you are right... the melay implementation will save 1 state as the output of melay is function of present state and value of inputs.VLSI Encyclopediahttps://www.blogger.com/profile/16627288764130002695noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-13243256676200288082015-03-02T15:03:16.335-08:002015-03-02T15:03:16.335-08:00If suppose we draw a mealy FSM for this detector, ...If suppose we draw a mealy FSM for this detector, I guess we would be saving one extra state as instead of going from S3 to S4 the FSM can go to the state S1, for detecting the overlapping sequence 1011, the last digit 1 can serve as the beginning of new sequence 1011, am I right?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-54913177545769045412014-06-09T14:24:37.590-07:002014-06-09T14:24:37.590-07:00why is the S_out for states S1 and S3 1? Should th...why is the S_out for states S1 and S3 1? Should they not be 0?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-35678770297810990052014-03-24T19:18:12.063-07:002014-03-24T19:18:12.063-07:00Vamsi, Thanks for writing.
You are correct, the se...Vamsi, Thanks for writing.<br />You are correct, the sensitivity list should also contain input s_in.Team VLSI Encyclopediahttp://www.vlsiencyclopedia.com/noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-86585155430838658942014-03-23T19:35:09.982-07:002014-03-23T19:35:09.982-07:00Here the second process will not be executed if th...Here the second process will not be executed if the s_in in the first clock cycle is 0. The sate machine will not move forward as processes react to only events and there will never be an event on Current_State. Sorry if i am wrong.Anonymoushttps://www.blogger.com/profile/03365448641117425029noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-54147818425281071282014-01-14T15:44:15.591-08:002014-01-14T15:44:15.591-08:00thank you !thank you !Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-67937035950456149712013-12-24T04:28:32.599-08:002013-12-24T04:28:32.599-08:00totally right!totally right!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-69874848891879983102013-11-12T05:19:59.484-08:002013-11-12T05:19:59.484-08:00after "end case;", there is an "en...after "end case;", there is an "end if;" too much, i thinkAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-86948285073500764872013-10-30T03:02:04.622-07:002013-10-30T03:02:04.622-07:00Thanks for appreciation :) Thanks for appreciation :) Team Vlsiencyclopedianoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-92186432253799473362013-10-29T14:02:51.431-07:002013-10-29T14:02:51.431-07:00very goodvery goodAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-11375273203014878922013-09-12T09:59:36.096-07:002013-09-12T09:59:36.096-07:00Thanks, there was a typo in the code... We updated...Thanks, there was a typo in the code... We updated it.<br /><br />Regards,<br />Team VLSI EncyclopediaVLSI Encyclopediahttps://www.blogger.com/profile/16627288764130002695noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-82408180329885094702013-09-12T03:06:07.259-07:002013-09-12T03:06:07.259-07:00Hi, Where is the "output state" logic de...Hi, Where is the "output state" logic defined to detect the sequence "1011"Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-88883040548993691892013-05-20T03:53:01.581-07:002013-05-20T03:53:01.581-07:00was in search of it..thank u..:)
was in search of it..thank u..:)<br />Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-16503687109420380562013-05-11T15:58:29.504-07:002013-05-11T15:58:29.504-07:00helped me alot, thanks :)helped me alot, thanks :)Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-79081524392643808852013-05-04T12:56:54.686-07:002013-05-04T12:56:54.686-07:00Love it.Love it.Confuciushttps://www.blogger.com/profile/04722451222100188200noreply@blogger.comtag:blogger.com,1999:blog-4978237314452270227.post-49901143692639540762013-04-30T01:04:30.508-07:002013-04-30T01:04:30.508-07:00superb :)
i totally understand the programming.
th...superb :)<br />i totally understand the programming.<br />thanks a lot.Anonymousnoreply@blogger.com