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Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Monday, 10 August 2020

Useful Vim plug-in for efficient coding in Perl

Think of a plug-in with which you can do the following while coding a Perl script:

  • Auto addition of file header
  • Easy addition of function/frame comment
  • Quick inclusion of default code snippet
  • Performing syntax check
  • Reading documentation about a function
  • Converting a full code block to comment, and vice versa
  • Help to speed up the code writing with consistency in coding.
One-stop solution for all these things is a perl-support vim plug-in

The Perl-Support Vim Plugin – Perl-IDE offers the easiest way to do all of the above, saving a lot of time and keystrokes.

We have already discussed in an earlier article regarding Use of Scripting languages in VLSI

We will be covering the following in this article

1. How to install perl-support plugin to use it with VIM.

2. Powerful features of the Perl-support plugin.


Steps to install Perl-Support VIM Plug-in


1. Download the plugin from the vim.org website.

Click here to download to go to the download page

Alternatively use below command

cd /usr/src/
wget http://www.vim.org/scripts/download_script.php?src_id=9701

2. Copy the zip archive perl-support.zip to $HOME/.vim and run below command

  unzip perl-support.zip

This command will create following files:

  $HOME/.vim/autoload/mmtemplates/...

  $HOME/.vim/doc/...

  $HOME/.vim/plugin/perl-support.vim

3. Loading of plug-in files must be enabled in $HOME/.vimrc. If not use previously

  filetype plugin on

Create .vimrc if there is none or use the files in $HOME/.vim/perl-support/rc as a starting point.


After done with installation lets get to know about

The Powerful Features of Perl-support


1. Add Automatic Header to *.pl file whenever you create a new file

2. Insert statements

3. Insert frequently used statements

4. Insert special variables

5. insert code snippets and manage templates

6. Run a profiler

7.  Run the script, check the syntax, start the debugger

8. Make integration


Details of all these can be found at 



Thursday, 6 August 2020

Use of Scripting languages in VLSI


Very often we come across questions from VLSI engineers that "Which scripting language should a VLSI engineer should learn?".

Well, Shell, Tcl, Perl, and Python are the scripting languages that are commonly used for VLSI front end/back end design automation and related applications. 

TCL: Tcl (pronounced "tickle" or as an initialism) is a high-level, general-purpose, interpreted, dynamic programming language

PERL: Practical Extraction and Reporting Language

PYTHON: Python is a dynamic, object-oriented, high-level programming language that can be used for many kinds of software development/scripting.

Shell Scripting: A shell script is a computer program designed to be run by the Unix/Linux shell which could be one of the following:

The Bourne Shell / The C Shell / The Korn Shell / The GNU Bourne-Again Shell

A shell is a command-line interpreter and typical operations performed by shell scripts include file manipulation, program execution, and printing text.
 
Perl has been in use for several years, but python is increasingly becoming more popular. In the past, we have already shared out views on the advantages of Python. Ref: Advantages of Python over Perl

Tcl is also used mostly for tool interfaces as several EDA tools support that.

If you know any kind of programming, learning a new scripting language will be easy.

Following are some commonly used applications of scripting languages in VLSI:
  • Front end RTL/Testbench code compilation and simulation flows
  • Automation of running tests in regressions, generating reports, analyzing failures, debug automation
  • Connectivity checks, netlist parsing, automatic generation/modification any RTL module/stubs, etc
  • Synthesis, P&R tools interfacing, and back end flow.
  • Several project management utilities - regression pass rates, trends, bug charts, etc - that helps in tracking projects
  • Any other task that is repetitive in workflow and can be automated.
Here is a complete comparison of TCL, PYTHON and PERL.

Monday, 3 August 2020

UPF - Unified Power Format

This is in continuation of our previous post on Low Power Design Techniques, where we learned about different types of strategies used to reduce the power consumption in integrated circuits. Here we will discuss about UPF (Unified Power Format). We will learn the following related to UPF.

What is UPF?
When does it started?
How to use UPF in design?
Who supports it?

The below flow shows the stages of design flow and where UPF is used.


What is UPF?
The Unified Power Format (UPF). It is intended to ease the job of specifying, simulating, and verifying IC designs that have a number of power states and power islands.

Unified Power Format (UPF) is an industry-wide power format specification to implement low power techniques in a power-aware design flow. UPF is designed to reflect the power intent of a design at a relatively high level. UPF scripts help describe power intent such as:

* Which power rails to be routed to individual blocks.
* When blocks are expected to be powered up or shut down. 
* How voltage levels should be shifted between two different power domains. 
* And type of measures taken for memory cells and retention registers contents if the primary power supply to a domain is removed. 

Hence making the design to be more power-efficient. With power becoming an important factor in today's electronic systems, there is a need for a more systematic approach to reduce the power in complex designs; and UPF is developed to address this need.

When does it started?
A Unified Power Format (UPF) technical committee was formed by the Accellera organization, chaired by Stephen Bailey of Mentor Graphics. As a reaction to the Power Forward Initiative, the group was proposed in July 2006 and met on September 13, 2006.[1] It submitted its first draft in January 2007, and a version 1.0 was approved to be published on February 26, 2007. Joe Daniels was a technical editor.

How to use UPF in design?
Tcl, the tool control language is the backbone of UPF, as well as the similar Common Power Format (CPF), Tcl is a scripting language originally created to provide a way to automate the control of design software.

The attraction of Tcl is that command-line commands can be used as statements in a script. Most Tcl implementations are specific to an individual tool. However, the CPF and UPF definitions are unusual in that they are meant to be used with all tools in a power-aware flow – the tools themselves have to determine whether the commands supplied in the Tcl script are relevant to them or not.

The Tcl command “create_power_domain”, for example, is used by UPF-aware tools to define a set of blocks in the design that are treated as one power domain that is supplied differently to other blocks on the same chip. The idea behind this type of command is that power-aware tools read in the description of which blocks in a design can be powered up and down independently. The tools can use that information to determine, for example, how the simulation will behave under different conditions.

For example, a testbench written in SystemVerilog may identify to the simulator that a particular block should be powered down to ensure that other blocks do not access it without checking on power status first.

A transistor-level simulation may use the power definitions to see what happens when supply voltages or substrate bias voltages change. Do all the necessary logic paths meet expected timing when the supply voltage to one block is lowered to save power while others are running at their maximum voltage? Similarly, a static analysis tool may check that the correct level shifters are in place to determine whether blocks in different power domains can communicate.

Who support it?
A number of EDA vendors have chosen to support UPF in their flows, including Mentor Graphics and Synopsys. However, support is not universal. Cadence Design Systems supports the Common Power Format originally developed by the company but which is now administered by the Silicon Integration Initiative but has declared support for the latest version of IEEE 1801, which incorporates a number of features from CPF.

Let us know in the comments if you wish to know about any specific details regarding UPF.

Thursday, 2 April 2020

Understanding Logic gates at transistor level : Not Gate

Today we will talk about some basics of digital logic gates. It's about using the transistor for the construction of logic gates. Transistors are used in the construction of logic gates as they act as fast switches. 
When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to the emitter may be near zero and can be used to construct gates for the TTL logic family. Let's start with simple NOT gate.

1. Not Gate using transistor



NOT gates are single-input devices which have an output level that is normally at logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level “1”, in other words, it “inverts” (complements) its input signal. The output from a NOT gate only returns “HIGH” again when its input is at logic level “0” giving us the Boolean expression A = Q.

The input of the NOT Gate is connected at the base of the transistor and the output is taken from the collector. The transistor here acts as the switch so when the voltage is applied at the base of the transistor the transistor starts conducting and shorts the output to the ground similarly when no voltage is applied at the input the output is connected to the Vcc as shown thus in this way the circuit implements the NOT function.