UVM Interview Questions - 5

Q31: What is virtual sequencer and virtual sequence in UVM?

A virtual sequencer is a sequencer that is not connected to a driver itself, but contains handles for sequencers in the testbench hierarchy. It is an optional component for running of virtual sequences - optional because they need no driver hookup, instead calling other sequences which run on real sequencers.

A sequence which controls stimulus generation across more than one sequencer, coordinate the stimulus across different interfaces and the interactions between them. Usually the top level of the sequence hierarchy i.e. 'master sequence' or 'coordinator sequence'. Virtual sequences do not need their own sequencer, as they do not link directly to drivers. When they have one it is called a virtual sequencer.

Here is a good article which explains how to use virtual sequence and virtual sequencer.

http://www.learnuvmverification.com/index.php/2016/02/23/how-virtual-sequence-works-part-1/


Q32: How set_config_* works?

The uvm_config_db class provides a convenience interface on top of the uvm_resource_db to simplify the basic interface that is used for configuring uvm_component instances.

Configuration is a mechanism in UVM that higher level components in a hierarchy can configure the lower level components variables. Using set_config_* methods, user can configure integer, string and objects of lower level components. Without this mechanism, user should access the lower level component using hierarchy paths, which restricts re-usability.

This mechanism can be used only with components. Sequences and transactions cannot be configured using this mechanism. When set_config_* method is called, the data is stored w.r.t strings in a table. There is also a global configuration table.

Higher level component can set the configuration data in level component table. It is the responsibility of the lower level component to get the data from the component table and update the appropriate table.

following are the method to configure integer, string and object of uvm_object based class respectively.

function void set_config_int (string inst_name, string field_name, uvm_bitstream_t value)

function void set_config_string (string inst_name, string field_name, string value)

function void set_config_object (string inst_name, string field_name, uvm_object value, bit clone = 1)

Q33: What are the advantages of uvm RAL model ?

  • The RAL (register abstraction layer) provides accesses to DUT and also keeps a track of register content of DUT.
  • UVM RAL can be used to automate the creation of high level, object oriented abstraction model of registers and memory in DUT.
  • Register layer makes the register abstraction and access of its contents independent of the bus protocol which is used to transfer data in and out of registers inside the design.
  • Hierarchical model provided by RAL makes the reusability of test bench components very easy.
  • The changes in initial configuration of registers or specifications can be easily communicated in the entire environment. RAL layer supports both front door and backdoor access. The backdoor access does not use the bus interface rather it uses the HDL defined paths for direct communication with the device. Thus in zero simulation time the registers of device can be reconfigured using the backdoor access and verification can be started.
  • One more advantage of backdoor access is that it can be used for verify if the access through front door are happening correctly. To achieve this the front door, write is verified using backdoor read.

Q34: What are the different override types?

Two type of overriding is supported by UVM

1. Type overriding

Type overriding means that every time a component class type is created in the Testbench hierarchy, a substitute type i.e. derived class of the original component class, is created in its place. It applies to all the instances of that component type.

Syntax:
<original_type>::type_id::set_type_override(<substitute_type>::get_type(), replace);

where “replace” is a bit which is when set equals to 1, enables the overriding of an existing override else existing override is honoured.

2. Instance overriding

In Instance Overriding, as name indicates it substitutes ONLY a particular instance of the component OR a set of instances with the intended component. The instance to be substituted is specified using the UVM component hierarchy.

Syntax:
<original_type>::type_id::set_inst_override(<substitute_type>::get_type(), <path_string>);

Where “path_string” is the hierarchical path of the component instance to be replaced.

Q35: Explain end of simulation in UVM?
Different approaches to finish the UVM Test using the objection mechanism are
1. Raising & dropping objections
raise_objection() and drop_objection() are the methods to be used to do that.
2. phase_ready_to_end
phase_ready_to_end method is executed automatically by UVM once ‘all dropped’ condition is achieved during Run Phase.
3. set_drain_time
Another approach supported by UVM is setting the drain time for the simulation environment. Drain time concept is related to the extra time allocated to the UVM environment to process the left over activities e.g. last packet analysis & comparison etc after all the stimulus is applied & processed.

IBM steps forward to replace Silicon Transistors with Carbon Nanotubes

Carbon Nanotube
Carbon Nanotube
The breakthrough is that - IBM improves carbon nanotube scaling below 10nm. How ever before calling it as breakthrough we should also check out what other giants like Intel, AMD, TSMC or Samsung is working on. This breakthrough has relation with the Moore's Law. Yes you got right..!!It says that the transistor counts double only every 18 month or so. It’s the time that Intel marks 40 years of the 4004 microprocessor and here now lying some fear that progress will soon hit a wall.

You can refer to my post History and Evolution of Integrated Circuits where it shows clear progress of semiconductor industry.

But not to worry, IBM has developed a way that could help the semiconductor industry continue to make ever more dense chips to support Moore's law. These chips will be both faster and more power efficient.

Few glimpse of carbon nanotube transistors

  • Carbon nanotube transistors can operate at ten nanometers
  • Equivalent to 10,000 times thinner than a strand of human hair
  • Less than half the size of today’s leading silicon technology
  • Could also mean wearables that attach directly to skin and internal organs


Here I have an animation for Animated Nanofactory in Action.

As a result of this the devices will become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now.

These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away.

A project at IBM is now aiming to have transistors built using carbon nanotubes ready to take over from silicon transistors soon after 2020. According to the semiconductor industry’s roadmap, transistors at that point must have features as small as five nanometers to keep up with the continuous miniaturization of computer chips.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology.

IBM's new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip, pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry.

By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

IBM’s chosen design uses six nanotubes lined up in parallel to make a single transistor. Each nanotube is 1.4 nanometers wide, about 30 nanometers long, and spaced roughly eight nanometers apart from its neighbors. Both ends of the six tubes are embedded into electrodes that supply current, leaving around 10 nanometers of their lengths exposed in the middle. A third electrode runs perpendicularly underneath this portion of the tubes and switches the transistor on and off to represent digital 1s and 0s.

The IBM team has tested nanotube transistors with that design, but so far it hasn't found a way to position the nanotubes closely enough together, because existing chip technology can’t work at that scale. The favored solution is to chemically label the substrate and nanotubes with compounds that would cause them to self-assemble into position. Those compounds could then be stripped away, leaving the nanotubes arranged correctly and ready to have electrodes and other circuitry added to finish a chip.

International Conference on VLSI Design and Embeded Systems - Jan 2016


Friends, get yourself ready for the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems which will be held during January 4-8, 2016 at Kolkata, West Bengal, India.

The theme for the conference this year is "Technologies for a Safe and Inclusive World". This 5 day conference comprises: first three days (January 4 to 6, 2016) of main conference followed by Tutorials during the last two days (January 7-8, 2016).

The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Today semiconductor technology is poised to look beyond its traditional bastions of application with pervasive impact on healthcare, environment, energy, transportation, and disaster management. The 29th International Conference on VLSI Design and the 15th International Conference on Embedded Systems will bring together industry and academia to present front-end technology under the theme of Technologies for a Safe and Inclusive World.

The Technical tracks will be grouped under the theme track and the three broad categories namely, Design Methodologies and Technology, Design Tools and EDA and Embedded System Design and Tools. The conference proceedings will be published by the IEEE Computer Society Press. Selected papers from this conference will also be published as special issues of top archival journals. 

Authors are invited to submit full-length (6 pages maximum) in IEEE CS proceedings format, original, unpublished papers with an abstract (200 words maximum) under the tracks listed below. To enable double blind review, the author list should be omitted from the main document. Papers violating length and blind-review criteria would be excluded from the review process. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered for publication. 

Track: Design Methodology and Technology 
D1: System-level Design 
ESL, System-level design methodology, Multicore systems, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect tolerant architectures 

D2: Advances in Digital Design 
Logic and Physical synthesis; Place & Route, Clock Tree, Physical Verification, Timing and Signal integrity, Power analysis and integrity, OCV, DFM; DFY; Challenges for advanced technology nodes 

D3: Analog / RF Design 
Analog Mixed Signal IP; High-Speed interfaces; SDR and wireless; Low-power Analog and RF; Effective use of Spectrum; Memory Design, Standard Cell Design 

D4: Power Aware Design 
Low-power design, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools 

D5: Devices / Circuits 
New Devices and architectures; Low power devices; Modeling and Simulation; Multi-domain simulation; Numerical methods; Device/circuit level variability models; Reliability simulation 

D6: Emerging Technologies 
Nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Nano-electronics and Nano-circuits, Nano-sensors, MEMS applications, Nano-assemblies and Devices, Non-classical CMOS; Post-CMOS devices; Biomedical circuits, Carbon Nano-tubes based computing 

Track : Design Tools and EDA 
T1: Design Verification 
Functional Verification; Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies 

T2: Test Reliability and Fault-Tolerance 
DFT, Fault modelling/simulation; ATPG; Low Power DFT; BIST & Repair; Delay test; Fault tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test; static and dynamic defect- and fault-recoverability, and variation-aware design 

T3: Computer-Aided Design (CAD) 
Hardware/software co-design, logic and behavioural synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction) 

Track : Embedded System Design and Tools 
E1: Embedded Systems 
Hardware/Software co-design & verification; Reconfigurable computing; Embedded multi-cores SOC and systems; Embedded software including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip; Embedded applications, Platforms & Case studies 

E2: FPGA Design and Reconfigurable Systems 
FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping 

E3: Wireless Systems 
Wireless Sensor Networks, Low Power wireless Systems, Embedded Wireless, Wireless protocols, Wireless Power / Charging 

Theme Track : Technologies for a Safe and Inclusive World 
H1: Technologies for Healthcare Applications 
H2: Technologies for Smart Management of Energy Systems 
H3: Technologies for Intelligent and Secure Transportation Systems 
H4: Technologies for Safety Assurance of Embedded Circuits and Systems 
H5: Technologies for Secure Embedded Circuits and Systems 


Proposals for Tutorials and Special Sessions/Panel Discussion on the above-listed topics (but not limited to) are invited. Please check conference website for details. 

Important dates are the following: 

REGULAR PAPERS 
Abstract submission : July 19, 2015 (Sunday) 
Full Paper submission : July 26, 2015 (Sunday) 
Acceptance Notification : Sep 26, 2015 (Saturday) 
Camera-ready version : Oct 11, 2015 (Sunday) 

TUTORIALS 
Tutorial Proposals : July 19, 2015 (Sunday) 
Acceptance Notification : Sep 26, 2015 (Saturday) 
Presentation Slides : Nov 15, 2015 (Sunday) 

SPECIAL SESSIONS 
Proposal submission : July 19, 2015 (Sunday) 
General Chairs 
Pradip Bose, IBM 
Susmita Sur-Kolay, ISI 

Vice-General Chairs 
Indranil Sengupta, IITKGP 
Parthasarathi Dasgupta, IIMC 

Program Chairs 
Krishnendu Chakrabarty, Duke 
Pallab Dasgupta, IITKGP 
Partha P. Das, IITKGP 

Tutorial Chairs 
Hafizur Rahaman, IIEST 
Prabhat Mishra, UF 
Annajirao Garimella, Intel 

Publiciy chairs 
Chandan Giri, IIESTS 
Ken Stevens, U. Utah 
Monica Pereira, UFRN 
Robert Wille, U. Bremen 
Swarup Bhunia, CWRU 
T. -Y. Ho, NCKU

SVEditor - A SystemVerilog Editor Eclipse Plugin

Source code editors have features specifically designed to simplify and speed up input of source code, such as syntax highlighting, indentation, autocomplete and bracket matching functionality. Variety of source code editors are available for VLDH, Verilog & SystemVerilog. We have already posted feb of them like Scriptum, and Emacs. 

You might be interested in : 



SVEditor is an Eclipse-based IDE (integrated development environment) for SystemVerilog and Verilog development. It provides a colourising editor for SystemVerilog with support for source navigation, content assist, source indent and auto-indent, SystemVerilog source templates and context-sensitive viewing of source documentation. Users have praised SVEditor for some of its features, such as searching for a colourisation of SystemVerilog keywords or words in a directory, auto-completion and some content assist. We believe that you can use SVEditor for debugging if you love emacs. Quoting from sourceforge.net, one user has said, “I’m totally stoked that this project is under active development. The tool is already very useful.

SVEditor provides a variety of features to make developing designs and testbench environments in SystemVerilog simpler and more efficient.

Features at a glance
The application uses a scanner that is similar to ctags for extracting the information from SystemVerilog and Verilog source files. It is engineered to be tolerant of errors, as well as to ignore unrecognized language constructs.

Among some of SVEditor’s features, we can mention colorizing for SystemVerilog keywords, outline view linked with editor, file structure view, SystemVerilog source index, syntax coloring editor, content assist, and cross-linking between data structure usage and declaration.

There are multiple ways to install the SVEditor software on your GNU/Linux computer, considering the fact that we’ve already installed the latest JRE (Java Runtime Environment) and Eclipse IDE software.

For exemple, you can download the latest version of the project as a JAR archive that can be opened into an existing Eclipse environment, you can search the application in the main software repositories of your GNU/Linux distribution, or compile it yourself using the source package provided right here on Softpedia.

For more details, do not hesitate to check out the project’s website.

Supported operating systems:

Taking a look under the hood of the SVEditor application, we can notice that it has been written entirely in the Java programming language and integrates with the Eclipse IDE for its graphical user interface.

If you don't have Eclipse IDE installed then here is link to download page of Eclipse IDE. Download Eclipse IDE

Being written in Java, SVEditor is a cross-platform software that runs on all operating ssytems where the Java Runtime Environment and Eclipse IDE are available, including GNU/Linux, Microsoft Windows and Mac OS X. It has been successfully tested on computers supporting either of the 64-bit (x86_64) or 32-bit (x86) CPU architectures.

UVM Interview Questions - 4

Q26: What is p_sequencer ? OR Difference between m_sequencer and p_sequencer?

m_sequencer is the default handle for uvm_vitual_sequencer and p_sequencer is the hook up for child sequencer.

m_sequencer is the generic uvm_sequencer pointer. It will always exist for the uvm_sequence and is initialized when the sequence is started.

p_sequencer is a typed-specific sequencer pointer, created by registering the sequence to the sequencer using macros (`uvm_declare_p_sequencer) . Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, etc.). p_sequencer will not exist if we have not registered the sequence with the `uvm_declare_p_sequencer macros.

The drawback of p_sequencer is that once the p_sequencer is defined, one cannot run the sequence on any other sequencer type.


Q27: What is the difference between Active mode and Passive mode with respect to agent?

An agent is a collection of a sequencer, a driver and a monitor.

In active mode, the sequencer and the driver are constructed and stimulus is generated by sequences sending sequence items to the driver through the sequencer. At the same time the monitor assembles pin level activity into analysis transactions.

In passive mode, only the monitor is constructed and it performs the same function as in an active agent. Therefore, your passive agent has no need for a sequencer. You can set up the monitor using a configuration object.

Q28: What is the difference between copy and clone?

The built-in copy() method executes the __m_uvm_field_automation() method with the required copy code as defined by the field macros (if used) and then calls the built-in do_copy() virtual function. The built-in do_copy() virtual function, as defined in the uvm_object base class, is also an empty method, so if field macros are used to define the fields of the transaction, the built-in copy() method will be populated with the proper code to copy the transaction fields from the field macro definitions and then it will execute the empty do_copy() method, which will perform no additional activity.

The copy() method can be used as needed in the UVM testbench. One common place where the copy() method is used is to copy the sampled transaction and pass it into a sb_calc_exp() (scoreboard calculate expected) external function that is frequently used by the scoreboard predictor.

The clone() method calls the create() method (constructs an object of the same type) and then calls the copy() method. It is a one-step command to create and copy an existing object to a new object handle.

Q29: What is UVM factory? 

UCM Factory is used to manufacture (create) UVM objects and components. Apart from creating the UVM objects and components the factory concept essentially means that you can modify or substitute the nature of the components created by the factory without making changes to the testbench. 

For example, if you have written two driver classes, and the environment uses only one of them. By registering both the drivers with the factory, you can ask the factory to substitute the existing driver in environment with the other type. The code needed to achieve this is minimal, and can be written in the test.

Q30: What are the types of sequencer? Explain each?

There are two types of sequencers :

uvm_sequencer #(REQ, RSP) :
When the driver initiates new requests for sequences, the sequencer selects a sequence from a list of available sequences to produce and deliver the next item to execute. In order to do this, this type of sequencer is usually connected to a driver uvm_driver #(REQ, RSP).

uvm_push_sequencer #(REQ, RSP) :
The sequencer pushes new sequence items to the driver, but the driver has the ability to block the item flow when its not ready to accept any new transactions. This type of sequencer is connected to a driver of type uvm_push_driver #(REQ, RSP).


UVM Interview Questions - 3

Q21: What is analysis port?

Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method write implemented in another component, specifically a subscriber.

port, export, and imp classes used for transaction analysis.

uvm_analysis_port
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.
uvm_analysis_imp
Receives all transactions broadcasted by a uvm_analysis_port.
uvm_analysis_export
Exports a lower-level uvm_analysis_imp to its parent.


Q22: What is TLM FIFO?

In simpler words TLM FIFO is a FIFO between two UVM components, preferably between Monitor and Scoreboard. Monitor keep on sending the DATA, which will be stored in TLM FIFO, and Scoreboard can get data from TLM FIFO whenever needed.

// Create a FIFO with depth 4
      tlm_fifo = new ("uvm_tlm_fifo", this, 4);


Q23: How sequence starts?
start_item starts the sequence

virtual task start_item ( uvm_sequence_item item,  
                                          int  set_priority =  -1,
                                        uvm_sequencer_base  sequencer =  null )

start_item and finish_item together will initiate operation of a sequence item.  If the item has not already been initialized using create_item, then it will be initialized here to use the default sequencer specified by m_sequencer. 

Q24: What is the difference between UVM RAL model backdoor write/read and front door write/read ?

Fontdoor access means using the standard access mechanism external to the DUT to read or write to a register. This usually involves sequences of time-consuming transactions on a bus interface. 

Backdoor access means accessing a register directly via hierarchical reference or outside the language via the PLI. A backdoor reference usually in 0 simulation time.

Q25: What is objection?

The objection mechanism in UVM is to allow hierarchical status communication among components which is helpful in deciding the end of test.

There is a built-in objection for each in-built phase, which provides a way for components and objects to synchronize their testing activity and indicate when it is safe to end the phase and, ultimately, the test end.

The component or sequence will raise a phase objection at the beginning of an activity that must be completed before the phase stops, so the objection will be dropped at the end of that activity. Once all of the raised objections are dropped, the phase terminates.

Raising an objection: phase.raise_objection(this);
Dropping an objection: phase.drop_objection(this);

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UVM Interview Questions - 1

Q11: Difference between module & class based TB?

Ans: A module is a static object present always during of the simulation.
A Class is a dynamic object because they can come and go during the life time of simulation.

Q12: What is uvm_config_db ? What is difference between uvm_config_db & uvm_resource_db?

Ans: uvm_config_db is a parameterized class used for configuration of different type of parameter into the uvm database, So that it can be used by any component in the lower level of hierarchy.

uvm_config_db is a convenience layer built on top of uvm_resource_db, but that convenience is very important. In particular, uvm_resource_db uses a "last write wins" approach. The uvm_config_db, on the other hand, looks at where things are in the hierarchy up through end_of_elaboration, so "parent wins." Once you start start_of_simulation, the config_db becomes "last write wins."

All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator
It is extended from the uvm_resource_db#(T), so it is child class of uvm_resource_db#(T)

Q13: What is the advantage and difference of  `uvm_component_utils() and `uvm_object_utils()?

Ans: The utils macros define the infrastructure needed to enable the object/component for correct factory operation. 

The reason there are two macros is because the factory design pattern fixes the number of arguments that a constructor can have. Classes derived from uvm_object have constructors with one argument, a string name. Classes derived from uvm_component have two arguments, a name and a uvm_component parent.  

The two `uvm_*utils macros inserts code that gives you a factory create() method that delegates calls to the constructors of uvm_object or uvm_component. You need to use the respective macro so that the correct constructor arguments get passed through. This means that you cannot add extra constructor arguments when you extend these classes in order to be able to use the UVM factory.

Q14: Difference between `uvm_do and `uvm_rand_send ?

Ans: `uvm_do perform the below steps:
  1. create
  2. start_item
  3. randomize
  4. finish_item
  5. get_response (optional)

while `uvm_rand_send perform all the above steps except create. User needs to create sequence / sequence_item.

Q15: Difference between uvm_transaction and uvm_seq_item?

Ans: class uvm_sequence_item extends uvm_transaction

uvm_sequence_item extended from uvm_transaction only, uvm_sequence_item class has more functionality to support sequence & sequencer features. uvm_sequence_item provides the hooks for sequencer and sequence , So you can generate transaction by using sequence and sequencer , and uvm_transaction provide only basic methods like do_print and do_record etc .


UVM Interview Questions - 2

Q16: Is uvm is independent of systemverilog ?

Ans: UVM is a methodology based on SystemVerilog language and is not a language on its own.  It is a standardized methodology that defines several best practices in verification to enable  efficiency in terms of reuse and is also currently part of IEEE 1800.2  working group.

Q17: What are the benefits of using UVM?

Ans: Some of the benefits of using UVM are :

  • Modularity and Reusability – The methodology is designed as modular components (Driver, Sequencer, Agents , env etc) which enables reusing components across unit level to multi-unit or chip level verification as well as across projects.
  • Separating Tests from Testbenches – Tests in terms of stimulus/sequencers are kept separate from the actual testbench hierarchy and hence there can be reuse of stimulus across different units or across projects
  • Simulator independent – The base class library and the methodology is supported by all simulators and hence there is no dependence on any specific simulator
  • Better control on Stimulus generation – Sequence methodology gives good control on stimulus generation. There are several ways in which sequences can be developed which includes randomization, layered sequences, virtual sequences etc which provides a good control and rich stimulus generation capability.
  • Easy configuration – Config mechanisms simplify configuration of objects with deep hierarchy. The configuration mechanism helps in easily configuring different testbench components based on which verification environment uses it and without worrying about how deep any component is in testbench hierarchy
  • Factory mechanism – Factory mechanisms simplifies modification of components easily. Creating each components using factory enables them to be overridden in different tests or environments without changing underlying code base.


Q18: Can we have user defined phase in UVM?

Ans: In addition to the predefined phases available in uvm , the user has the option to add his own phase to a component. This is typically done by extending the uvm_phase class the constructor needs to call super.new which has three arguments
  • Name of the phase task or function
  • Top down or bottom up phase
  • Task or function


The call_task  or call_func and get_type_name need to be implemented to complete the addition of new phase.
Below is a simple example 

Example
class custom_phase extends uvm_phase;
   function new();
      super.new(“custom”,1,1);
   endfunction

   task call_task  ( uvm_component parent);
     my_comp_type comp;
     if ( $cast(comp,parent) )
             comp.custom_phase();
   endtask

   virtual function string get_type_name();
      return “custom”;
   endfunction
endclass


Q19: What is uvm RAL model ? why it is required ?

Ans: In a verification context, a register model (or register abstraction layer) is a set of classes that model the memory mapped behavior of registers and memories in the DUT in order to facilitate stimulus generation and functional checking (and optionally some aspects of functional coverage). The UVM provides a set of base classes that can be extended to implement comprehensive register modeling capabilities.

Q20: What is the difference between new() and create?

Ans: We all know about new() method that is use to allocate memory to an object instance. In UVM (and OVM), the create() method causes an object instance to be created from the factory. This allows you to use factory overrides to replace the desired object with an object of a different type without having to recode.

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UVM Interview Questions

Q1: What is UVM? What is the advantage of UVM?

Ans: UVM (Universal Verification Methodology) is a standardized methodology for verifying the both complex & simple digital design in simple way.

UVM Features:
  • First methodology & second collection of class libraries for Automation
  • Reusability through testbench
  • Plug & Play of verification IPs
  • Generic Testbench Development
  • Vendor & Simulator Independent
  • Smart Testbench i.e. generate legal stimulus as from pre-planned coverage plan
  • Support CDV –Coverage Driven Verification
  • Support CRV –Constraint Random Verification
  • UVM standardized under the Accellera System Initiative
  • Register modeling

Q2: UVM derived from which language?

Ans: Here is the detailed connection between SV, UVM, OVM and other methodologies. 



Q3. What is the difference between uvm_component and uvm_object?
                       OR
We already have uvm_object, why do we need uvm_component which is actually derived class of uvm_object?

Ans: 
uvm_component:
  • Quasi Static Entity (after build phase it is available throughout the simulation)
  • Always tied to a given hardware(DUT Interface) Or a TLM port
  • Having phasing mechanism for control the behavior of simulation
  • Configuration Component Topology

uvm_object:
  • Dynamic Entity (create when needed, transfer from one component to other & then dereference)
  • Not tied to a given hardware or any TLM port
  • Not phasing mechanism 

Q4: Why phasing is used? What are the different phases in uvm?

Ans: UVM Phases is used to control the behavior of simulation in a systematic way & execute in a sequential ordered to avoid race condition. This could also be done in system verilog but manually.
  1. List of UVM Phases:
  2. buid_phase
  3. connect_phase
  4. end_of_elaboration_phase
  5. start_of_simulation_phase       
  6. run _phase  (task)
    Sub Phases of Reset Phase:
    pre_reset_phase
    reset_phase
    post_reset_phase
    pre_configure_phase
    configure_phase
    post_configure_phase
    pre_main_phase
    main_phase
    post_main_phase
    pre_shutdown_phase
    shutdown_phase
    post_shutdown_phase
  7. extract_phase
  8. check_phase
  9. report_phase
Below figure makes it more clear



Q5: Which uvm phase is top - down , bottom – up & parallel?

Ans: Only build phase is a top-down & other phases are bottom-up except run phase which is parallel. The build phase works top-down since the testbench hierarchy may be configure so we need to build the branches before leafs

Q6: Why build phase is top – down & connect phase is bottom – up?

Ans: The connect phase is intended to be used for making TLM connections between components, which is why it occur after build phase. It work bottom-up so that its got the correct implementation all the way up the design hierarchy, if worked top-down this would be not possible

Q7: Which phase is function & which phase is task?

Ans: Only run phase is a task (time consuming phase) & other phases are functions (non-blocking)

Q8: Which phase takes more time and why?

Ans: As previously said the run phase is implemented as task and remaining all are function. run phase will get executed from start of simulation to till the end of simulation. run phase is time consuming, where the testcase is running.

Q9: How uvm phases initiate?

Ans: UVM phases initiate by calling run_test(“test1”) in top module. When run_test() method call, it first create the object of test top & then call all phases.

Q10: How test cases run from simulation command line?

Ans: In top module write run_test(); i.e. Don't give anything in argument.
Then in command line : +UVM_TESTNAME=testname

Intel's Skylarke Processors for PCs, Tablets and Servers

Intel is launching a full portfolio of "Skylake" processors that company officials expect will combine with Microsoft's Windows 10 operating system to help jump start a stagnant global PC market.

Executives with the chip maker for more than a year have been talking about the 14-nanometer Skylake architecture and the advanced features that are contained within it, touching on everything from graphics and imaging to security, memory, performance and wireless connectivity. In early August, Intel rolled out two Skylake chips—the Core i7-6700K and i5-6600K desktop processors—for gaming machines, and later in the month officials gave out a few more details during the Intel Developer Forum (IDF).

While Intel Corp. is going to release its code-named “Skylake” processors a little later than expected, the company keeps the plan to introduce its new micro-architecture for virtually all segments of the market continuum this year. Intel will roll-out “Skylake” central processing units for tablets, 2-in-1s, personal computers and servers this year, the chip giant confirmed this week.

“When I look at the range of what Skylake’s able to deliver from the Core M level all up to the i7 and Xeon, it’s just going to be a fantastic product,” said Intel CEO Brian Krzanich, in an interview with the IDG News Service at Mobile World Congress in Barcelona.

Intel ran into problems with production of its code-named “Broadwell” processors using 14nm manufacturing technology last year. Due to insufficient yields, the world’s largest maker of microprocessors had to delay introduction of its latest chips by about a year. However, since “Skylake” brings a lot of innovations, Intel did not want to delay it significantly. As a result, “Broadwell” products will have a relatively short lifecycle.

Intel will introduce the first “Skylake” processors in the form of dual-core Core M chips in the third quarter of this calendar year. The CPUs will power high-performance tablets, hybrid 2-in-1 personal computers and ultra-thin notebooks. It is expected that many mobile devices powered by Intel Core M “Skylake” will support Rezence wireless charging and WiGig short-range transmission technology.

In late Q3 or early Q4 the Santa Clara, California-based chip designer will introduce its first Core i3, Core i5 and Core i7 chips featuring “Skylake” micro-architecture for mainstream personal computers, including desktops and laptops. The lineup is projected to include chips with unlocked multiplier designed for enthusiast-class desktop PCs. Systems featuring the new “Skylake” processors will have improved storage performance thanks to native support of SATA Express. In addition, many “Skylake”-powered PCs will use DDR4 memory and support a variety of other innovations.



Intel also plans to introduce Xeon processors with “Skylake” cores for uniprocessor servers later this year. While there are plans to bring “Skylake” architecture to Xeon chips for dual-processor and multi-processor servers, Intel yet has to outline exact plans concerning the move.

Intel “Skylake” processors will be made using 14nm process technology and will feature a brand new micro-architecture that is designed to improve performance and power efficiency of central processing units. Unfortunately, not all “Skylake” processors will support 512-bit AVX 3.2 instructions, according to unofficial information.

Resistive Memory - ReRam

ReRam_Crossbar-Feature_vlsiencyclopedia

The memory tech that will eventually replace NAND flash, finally in market

What is ReRam?

ReRam is Resistive random-access memory (RRAM or ReRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material often referred to as a memristor. The biggest advantage of ReRAM technology is its good compatibility with CMOS technologies.

It is under development by a number of companies, and some have already patented their own versions of the technology. The memory operates by changing the resistance of special dielectric material called a memresistor (memory resistor) whose resistance varies depending on the applied voltage.

What makes ReRam?

From the viewpoint of the material choice, the advantage of ReRAM is evident. It is possible to fabricate MOM structures easily by using the oxides widely used in the current semiconductor technologies. Low-current ReRAM operation was reported in the CuOx-based MOM structure. The CuOx layer was grown by the thermal oxidation of the 0.18-μm Cu. NiO and CoO are being intensively studied as oxide materials for ReRAM, and these transition metal elements are also used in metal silicides employed as gate materials. Recently, the good scaling feasibility of ReRAM was demonstrated in an HfOx-based memory with a cell size of 30 nm. The devices in a 1-kbit array exhibited a high device yield (~100%) and robust cycling endurance (>106) with a pulse width of 40 ns. The memory cell consisted of a TiN/Ti/HfOx/TiN structure. Here, the Ti overlayer played the role of oxygen gettering for better ReRAM operation. The gettering effect has already been investigated in HfOx as a high-k material for the gate dielectric films in CMOS devices. The academic and technological knowledge about high-k materials will be very useful in the design of the stacking structure for a ReRAM device.

How ReRam Works?

RRAM is the result of a new kind of dielectric material which is not permanently damaged and fails when dielectric breakdown occurs; for a memresistor, the dielectric breakdown is temporary and reversible. When voltage is deliberately applied to a memresistor, microscopic conductive paths called filaments are created in the material. The filaments are caused by phenomena like metal migration or even physical defects. Filaments can be broken and reversed by applying different external voltages. It is this creation and destruction of filaments in large quantities that allows for storage of digital data. Materials that have memresistor characteristics include oxides of titanium and nickel, some electrolytes, semiconductor materials, and even a few organic compounds have been tested to have these characteristics.

The principal advantage of RRAM over other non-volatile technology is high switching speed. Because of the thinness of the memresistors, it has a great potential for high storage density, greater read and write speeds, lower power usage, and cheaper cost than flash memory. Flash memory cannot continue to scale because of the limits of the materials, so RRAM will soon replace flash memory.

Difference between simulation and emulation

Car_racing_simulator_-_SBR_Racing,_Construma,_2015.04.17A simulation is a system that behaves similar to something else, but is implemented in an entirely different way. It provides the basic behaviour of a system but may not necessarily abide by all of the rules of the system being simulated. It is there to give you an idea about how something works.

Think of a flight simulator as an example. It looks and feels like you are flying an airplane, but you are completely disconnected from the reality of flying the plane, and you can bend or break those rules as you see fit. E.g.; Fly an Airbus A380 upside down between London and Sydney without breaking it.

An emulation is a system that behaves exactly like something else, and abides by all of the rules of the system being emulated. It’s like duplicating every aspect of the original device’s behaviour. It is effectively a complete replication of another system, right down to being binary compatible with the emulated system's inputs and outputs, but operating in a different environment to the environment of the original emulated system. The rules are fixed, and cannot be changed or the system fails.

Today hardware emulation has become an very popular tool for verification because of following reasons:

In the past few years, the emulation user community has expanded exponentially by the addition of software developers to the traditional base of hardware designers and verification engineers. 

Also, uses of hardware emulation have multiplied because of its versatility as a resource for debugging both the hardware and software of complex system-on-chip (SoC) designs. Hardware emulation is the only verification tool that can be deployed in more than one mode. In fact, it can be used in four main modes, some of which can be combined for added versatility. Because of this resourcefulness, hardware emulation can be used to achieve several verification objectives.

Following are the deployment modes for hardware emulator. These are characterized by type of stimulus applied to DUT:

  • In Circuit Emulation (ICE) : This was considered to be the traditional method when hardware emulation was deployed. In this case, the DUT is mapped inside the emulator and connected in in-circuit emulation (ICE) mode to the target system in place of a chip or processor for debug prior to silicon availability.
  • Transaction Based Acceleration (TBX) : Transaction-based emulation moves verification up a level of abstraction from the register transfer level (RTL), improving performance and debug productivity. It’s gaining popularity over the ICE mode because the physical target system is replaced by a virtual target system using a hardware verification language (HVL) such as
    SystemVerilog, SystemC, or C++.
  • Simulation Testbench Acceleration : In this mode, an RTL testbench drives the DUT in the emulator via a programmable logic interface (PLI). In general, this is the slowest performance mode, but it has some advantages, such as the fact that it does not require changes to the testbench.
  • Embeded Software Acceleration : In this mode, the software code is executed on the DUT processor mapped inside the emulator. This is the fastest performance mode, making it the choice for processing billions of verification cycles necessary to boot an operating system.

It is possible to mix some of the above modes, such as processing embedded software together with a virtual testbench driving the DUT via verification IP or even in ICE mode.

IEEE Standards

vlsi-ieee802IEEE 802 refers to a family of IEEE standards dealing with local area networks and metropolitan area networks.

More specifically, the IEEE 802 standards are restricted to networks carrying variable-size packets. By contrast, in cell relay networks data is transmitted in short, uniformly sized units called cells. Isochronous networks, where data is transmitted as a steady stream of octets, or groups of octets, at regular time intervals, are also out of the scope of this standard. The number 802 was simply the next free number IEEE could assign, though “802” is sometimes associated with the date the first meeting was held — February 1980.

The services and protocols specified in IEEE 802 map to the lower two layers (Data Link and Physical) of the seven-layer OSI networking reference model. In fact, IEEE 802 splits the OSI Data Link Layer into two sub-layers named Logical Link Control (LLC) and Media Access Control (MAC), so that the layers can be listed like this:

  • Data link layer
  • LLC Sublayer
  • MAC Sublayer
  • Physical layer

The IEEE 802 family of standards is maintained by the IEEE 802 LAN/MAN Standards Committee (LMSC). The most widely used standards are for the Ethernet family, Token Ring, Wireless LAN, Bridging and Virtual Bridged LANs. An individual Working Group provides the focus for each area.

IEEE developed a set of 802 network standards. They include:

  • IEEE 802.1: Standards related to network management.
  • IEEE 802.2: General standard for the data link layer in the OSI Reference Model. The IEEE divides this layer into two sub-layers -- the logical link control (LLC) layer and the media access control (MAC) layer. The MAC layer varies for different network types and is defined by standards IEEE 802.3 through IEEE 802.5.
  • IEEE 802.3: Defines the MAC layer for bus networks that use CSMA/CD. This is the basis of the Ethernet standard.
  • IEEE 802.4: Defines the MAC layer for bus networks that use a token-passing mechanism (token bus networks).
  • IEEE 802.5: Defines the MAC layer for token-ring networks.
  • IEEE 802.6: Standard for Metropolitan Area Networks (MANs).

Ethernet–Introduction

VLSI_ETHERNETIn today's business world, reliable and efficient access to information has become an important asset in the quest to achieve a competitive advantage. File cabinets and mountains of papers have given way to computers that store and manage information electronically.

Computer networking technologies are the glue that binds these elements together. Networking allows one computer to send information to and receive information from another. We can classify network technologies as belonging to one of two basic groups. Local area network (LAN) technologies connect many devices that are relatively close to each other, usually in the same building. The library terminals that display book information would connect over a local area network. Wide area network (WAN) technologies connect a smaller number of devices that can be many kilometers apart.

In comparison to WANs, LANs are faster and more reliable, but improvements in technology continue to blur the line of demarcation. Fiber optic cables have allowed LAN
technologies to connect devices tens of kilometers apart, while at the same time greatly
improving the speed and reliability of WANs.

Read More >>

Ethernet

VLSI_ETHERNETEthernet has been a relatively inexpensive, reasonably fast, and very popular LAN technology for several decades. Two individuals at Xerox PARC -- Bob Metcalfe and D.R. Boggs -- developed Ethernet beginning in 1972 and specifications based on this work appeared in IEEE 802.3 in 1980. Ethernet has since become the most popular and most widely deployed network technology in the world. Many of the issues involved with Ethernet are common to many network technologies, and understanding how Ethernet addressed these issues can provide a foundation that will improve your understanding of networking in general.

The Ethernet standard has grown to encompass new technologies as computer networking has matured. Specified in a standard, IEEE 802.3, an Ethernet LAN typically uses coaxial cable or special grades of twisted pair wires. Ethernet is also used in wireless LANs. Ethernet uses the CSMA/CD access method to handle simultaneous demands. The most commonly installed Ethernet systems are called 10BASE-T and provide transmission speeds up to 10 Mbps. Devices are connected to the cable and compete for access using a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. Fast Ethernet or 100BASE-T provides transmission speeds up to 100 megabits per second and is typically used for LAN backbone systems, supporting workstations with 10BASE-T cards. Gigabit Ethernet provides an even higher level of backbone support at 1000 megabits per second (1 gigabit or 1 billion bits per second). 10-Gigabit Ethernet provides up to 10 billion bits per second.

The Ethernet standard has grown to encompass new technologies as computer networking has matured. Specified in a standard, IEEE 802.3, an Ethernet LAN typically uses coaxial cable or special grades of twisted pair wires. Ethernet is also used in wireless LANs. Ethernet uses the CSMA/CD access method to handle simultaneous demands. The most commonly installed Ethernet systems are called 10BASE-T and provide transmission speeds up to 10 Mbps. Devices are connected to the cable and compete for access using a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. Fast Ethernet or 100BASE-T provides transmission speeds up to 100 megabits per second and is typically used for LAN backbone systems, supporting workstations with 10BASE-T cards. Gigabit Ethernet provides an even higher level of backbone support at 1000 megabits per second (1 gigabit or 1 billion bits per second). 10-Gigabit Ethernet provides up to 10 billion bits per second.

 

A Cache Memory

Today we feel to revise what we know about cache memory. A cache is a memory device that improves performance of the processor by transparently storing data such that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere.



Access to cache can result in either one of the following: cache miss or cache hit.Cache hit means that the requested data is contained in the cache and cache miss means data is not found there in cache.On cache hit processor takes data from cache itself for processing.On cache miss the data is fetched from the original memory location.Cache memories are volatile and small in storage size.Since the storage size is small the address decoding takes less time and hence caches are faster then normal physical memories(RAM's) in computers.

As I said the data is stored transparently in cache.This means that the user who is requesting data from the cache need not know whether data is stored in cache or system memory.It is handled by the processor.The word cache means "conceal" in French.


A simple cache contains three fields.

1. An index which is local to the cache.
2. A tag which is the index with reference to the main memory.This will let the processor know the location in main memory where an exact copy of data is stored.
3. Data, which is actual data needed by the processor.


When processor needs some data from the memory it first checks in cache.It sees all the tag fields in the cache to see whether same data is available in cache.If the tag is found then the corresponding data is taken.Otherwise a cache miss error is asserted and the main memory is accessed.Also the cache memory is updated with the recent memory access.This is called cache update on cache miss.


During a cache update if the cache is full, then it has to delete a row.This is decided on a cache replacement algorithm.Some algorithms are:

1. LRU - Least recently used data is replaced.
2. MRU - Most recently used data is replaced.
3. Random replacement - Simple, used in ARM processors.
4. Belady's Algorithm - discards the data which may not be used for the longest time in future.Not perfectly implementable in practice.


The average memory access time of a cache enabled system can be calculated using the hit and miss ratio of a cache.

Average memory access time = (Time_cache * Hit_counts ) + ( (Time_cache + Time_mm) * Miss_counts)

where,
Time_cache and Time_mm is the time needed to access a location for cache and main memory respectively.
Hit_counts and Miss_counts are the hit and miss probabilities.


There are two types cache writing: write back(copy-back) and write through.

When the data at a particular memory location is updated then this data must be written back to cache.If the data is updated only in the cache then it is called write back.If the updating of data happens both in cache and main memory then it is called write through.Write through keeps the cache and memory synchronized.In the write back operation since the cache data is not same as the main memory data it is marked as "dirty" data.These dirty data will be written back into main memory when the particular data is cleared from the cache.If a miss happens in a write-back cache it may sometimes require two memory accesses to service : one to first write the dirty location to memory and then another to read the new location from memory.

The main memory locations may be altered without proper updating in cache by peripherals using DMA or by a multi core processor.This results in a out of date data in cache.These type of data is called "stale" data.To solve these stale data problems we have to use cache coherence protocols between the cache managers to keep the data consistent.


All caches are CAM(content accessible memory).And for efficiency we have to scan all the memory contents in one cycle.This requires parallel hardware.Also higher the memory size the more is the memory access time.

Let us see now,how a cache is made.Say we have a 32 bit main memory in our system and the cache chip size is 4 Kb.Also say each line in cache stores 32 bytes so that there are totally 128 lines.Each line in cache have two fields. Address(4 bytes) and Data.The address is further divided into two fields- Tag(27 bits) and offset(5 bits for indexing a particular byte among the data).Remember that the tag contain the MSB 27 bits of the address here.These kind of caches are called Fully associative caches.Since the tag is 27 bits(relatively long) it takes more time to read data from Fully associative cache.Also more hardware circuit is required for parallel reading of tags from the CAM type cache.So they are expensive but more efficient.

Fully associative cache


Another type of cache architecture is known as direct mapped cache.In this the address is divided into three fields named tag(20 bits),index(7 bits used as an index the 128 lines in cache) and offset(5 bits).The problem with this type of cache is that the cache is less efficient since the main memory cannot be copied to any line in cache as in fully associative cache.This is because the addresses with the same index will be mapped to the same line in cache.But the cache access time is less here.In certain situations you may get a cache miss for almost every access.So they are cheap but less efficient.

Direct mapped Cache
Another type of cache is called set associative cache which has the advantages of both direct mapped and fully associative caches.These are again subdivided based on the number of bits in the index field.

2. 2 way set associative cache - In this type of cache we have two group of lines,each containing 64 lines.The cache has the same number of fields as direct mapped cache but tag has 21 bits and index has 6 bits here.


2. 4 way set associative cache - Here we have 4 groups each contains 32 lines.index has 5 bits and tag has 22 bits.

2-way and 4-way set associative caches

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