- All state machine outputs shall always be registered
- Thou shalt use registers, never latches
- Thy state machine inputs, including resets, shall be synchronous
- Beware fast paths lest they bite thine ankles
- Minimize skew of thine clocks
- Cross clock domains with the greatest of caution. Synchronize thy sig- nals!
- Have no dead states in thy state machines
- Have no logic with unbroken asynchronous feedback lest the ﬂeas of myriad Test Engineers infest thee
- All decode logic must be crafted carefully—eschew asynchronicity
- Trust not thy simulator—it may beguile thee when thy design is junk
- An asynchronous active-low clear input sets the Q output to zero.
- It is triggered on the rising edge of the clock.
- A latch control that opens the latch when high (the latch is transparent).
- A maximum clock-to-out time under worst-case setup and hold time violations. This time is available in the library element speciﬁcations.
-- Now pass the synchronized toggle through another ﬂip-ﬂop
-- Finally XOR the two synchronized signals to create a pulse
The creation of state machines is a mixture of art and science. A well-crafted state machine will possess a sense of elegance; it will be appealing, both functionally and visually.
Here, a very simple example is presented as an illustration of state machine design. The state diagram for the Flintstones State Machine is shown in figure below popularly known as The Flintstones State Machine.
- The State Machine has two states, State Bed and State Rock.
- There is one output, Fred, which takes the value 0 in State Bed and 1 in State Rock.
- A reset, caused by a low level on Reset_n, puts the State Machine into State Bed.
- The State Machine waits in State Bed while Barney is low, and enters State Rock when Barney goes high.
- The State Machine then waits in State Rock while Wilma is low, and returns to State Bed when Wilma goes high.
An example implementation of the Flintstones State Machine is shown in Code Sample 7 below:
Notes on the State machine Implementation
- The reset signal (Sync_Reset_n) is synchronized with Clock_In before being sent to the State Machine.
- Barney and Wilma must also be synchronous to Clock_In; at the very least, there must be an assurance that the State Machine’s state and output regis- ter’s setup and hold times are not violated.
- This design assigns a default value to each output and to the state variable before entering the case statement. This ensures that only those signals that are not taking default (usually inactive) values need be listed in the case statement. This is optional; it is entirely reasonable to list every signal under each transition term, including inactive signals.
- Note that the output signal Fred comes directly from a D-type ﬂip-ﬂop: it is not a decode of the state variable. This ensures Fred’s cleanliness (so to speak).
- The “when others” in the case statement handles the possibility that the State Machine might end up in a dead state.