Modelsim Tips and Tricks

1. How to get rid of Std Arithmetic warnings around 0 ns?

    # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
    #    Time: 0 ns  Iteration: 1  Instance: /cordic_tb/uut/add3

    Simply turn the Std checking off in your  .do or .tcl script file, example:

    set StdArithNoWarnings 1
    run 0 ns;
    set StdArithNoWarnings 0
    # Continue script

2. How to get rid of Std Arithmetic warnings until my reset is asserted?

    If the warnings continue until a certain time or when a signal is asserted then the when statement can help out.

    Example: the Std warnings can be ignored until the signal reset_s is asserted

    when -label enable_StdWarn {reset_s == '1'} {echo "Enable StdArithWarnings" ; set StdArithNoWarnings 0 ;}

    Example: the Std warnings can be ignored until 3800 ns

    when -label enable_StdWarn {$now == @3800 ns} {echo "Enable StdArithWarnings" ; set StdArithNoWarnings 0 ;}

3. How to stop the simulator without using asserts?

    The usual way to stop the simulator is to use the assert statement in VHDL. However, not everybody likes the Failure/Error message in the transcript window.

    # ** Failure: End of Simulation
    #    Time: 360 ns  Iteration: 0  Process: /test_tb/line__35 File: test_tb.vhd

    An easy solution is the same construct as shown above. Simple add a signal to your testbench and assert this signal at the end of the simulation. Then use the when statement in your script to stop the simulator.

    Example: stop the simulator when the signal end_of_simulation='1'

    when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation" ; stop ;}

    # End of simulation
    # Simulation stop requested

    Note: for maximum portability to other simulators the assert statement is recommended method!

4. How to speed up simulation/reduce wlf file size?

    There are many ways to speed up simulation. If you are performing long simulation you can speed up the simulation by turning off the signal logging to the wlf file until you reach the time of interest.

    Example: Disable signal logging until time 4420 us

    nolog -all
    when -label start_logging {$now == @4420 us} {echo "Start logging " ; log -r *;}

Tip: how to find out what a ModelSim error message means

    Error messages and exit codes are described in the User's Manual, however a quick way to get this information is to use the verror command. Simply type verror #error_number to get a detailed description on the error number.


Related Posts:

1. Customize the ModelSim Wave View in the Xilinx ISE Simulation
2. Compiling Xilinx library for ModelSim simulator

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