Use SystemVerilog for coverage metrics

The design-and-verification industry is at the intersection of two important trends in the design and verification of SOC (system-on-chip) devices: the adoption of SystemVerilog HDVL (hardware-description and -verification language) and the increasingly critical role for coverage metrics. The interest in System Verilog is understandable; this IEEE-standard language has the features for RTL (register-transfer-level) design, high-level modeling, testbench creation, and assertion specification (Reference).

SystemVerilog also provides constructs for design-and-verification engineers to specify functional coverage points—conditions that designers must exercise for complete verification of the design. Designers increasingly use functional coverage to supplement traditional code coverage. The primary driver for this evolution is the widespread use of constrained-random-stimulus generation.

Traditional verification plans typically include a list of design features or tests that verify features and test status. This approach has worked well with handwritten, directed tests because of the clear correspondence between features and tests. However, verification consists of writing and running each test in simulation, perhaps after turning on some code coverage to help identify features you may have missed in the plan.

Constrained-random-stimulus generation requires a different approach, in which each automatically generated test can exercise many features and parts of the design. A modern verification plan lists features, functional coverage points for the features, and coverage status. You gauge verification closure by the number of coverage points you exercise rather than the number of tests you complete.

SystemVerilog provides all the features necessary to develop both handwritten tests and constrained-random testbenches and to track progress toward closure. Most simulators have built-in code coverage for the new design constructs that SystemVerilog introduces. Thus, code-coverage metrics are available for designs taking advantage of the language's advanced RTL features.

SystemVerilog provides several powerful specification methods for functional coverage. The first is cover property, which is part of the SVA (SystemVerilog Assertions) subset of the language. SVA's assertion features, including temporal sequences, are also available for functional coverage.
For example,

MiniMuM and MaxiMuM response
minimum_response: cover property (@(posedge clk)
(req ##1 ack ));
maximum_response: cover property (@(posedge clk)
(req ##5 ack ));

Above example ensures that the simulator exercises the two extremes—one and five cycles—of a request-acknowledge handshake. Both simulators and many formal-analysis tools support the cover-property construct. If formal analysis can prove that a coverage point is unreachable, a design bug may be blocking important functions from being exercised. If formal analysis instead provides a trace showing how to reach a coverage point, this trace can provide a good hint on how to write or generate a test.

Beyond individual coverage properties, you sometimes must track ranges of values. SystemVerilog provides the cover-group construct, which is not part of SVA, to perform this function.
For example,

PayLoad sizes of incoming Packets
minimum_response: cover property (@(posedge clk)
(req ##1 ack ));
maximum_response: cover property (@(posedge clk)
(req ##5 ack ));
covergroup payloads_seen (@(packet_received);
coverpoint payload_size {
bins empty = { 0 };
bins minimum = { 1 };
bins maximum= { 1023 };
bins others = default; }
endgroup : payloads_seen

Above example tracks the payload sizes of incoming packets on a network interface and ensures the coverage of corner cases of empty, minimum, and maximum payloads. SystemVerilog also provides the cross construct to measure cross-coverage between two coverage points. This feature allows the tracking of combinations of coverage metrics.
For example,

EnumEratEd typE for four packEt cLassEs

enum { read, write, atomic, ctrl } packet_class;
covergroup packets_seen (@(packet_received);
coverpoint payload_size {
bins empty = { 0 };
bins minimum = { 1 };
bins maximum= { 1023 };
bins others = default; }
coverpoint packet_class;
cross payload_size, packet_class;
endgroup : packets_seen

Above example specifies an enumerated type for four packet classes for the network interface, adds a cover point to track the packet classes, and crosses the packet types with the payload sizes.

Ultimately, the SOC-tapeout decision must take into account all coverage metrics. Although functional coverage is the primary method, code coverage has value as a backup to identify areas of the design with no functional coverage due to an incomplete verification plan. The project team needs to merge together code- and functional-coverage results to assess verification progress and help determine verification closure. Coverage is critical for modern, constrained-random verification. Without effective metrics, no reliable way exists to gauge status and manage progress. In addition to its other features and benefits, SystemVerilog provides support for functional coverage. By including coverage in the verification plan from the start of the project and taking advantage of SystemVerilog, the SOC team can employ a complete plan-to-closure methodology that greatly increases the chances for a successful product.

3D IC market to see stable growth through 2016

The global 3D integrated circuit market is forecast to grow by 19.7 percent between 2012 and 2016, with the major growth driver being strong demand for memory products, particularly flash memory and DRAM.

3D integrated circuits help improve the performance and reliability of memory chips, and as an added benefit the resulting chips are smaller and cheaper. However, chips based on 3D circuits face thermal conductivity problems which might pose a challenge to further growth.

According to Infiniti Research, the biggest 3D IC vendors at the moment are Advanced Semiconductor Engineering (ASE), Samsung., STMicroelectronics and Taiwan Semiconductor Manufacturing Co. (TSMC). IBM, Elpida, Intel and Micron are also working on products based on 3D ICs.

Intel was a 3D IC pioneer and it demoed a 3D version of the Pentium 4 back in 2004. The overly complicated chip offered slight performance and efficiency improvements over the 2D version of the chip, which really isn't saying much since Prescott-based Pentium 4s were rubbish.

The focus then shifted on memory chips and some academic implementations of 3D processors, but progress has been relatively slow, hence any growth is more than welcome.

SystemVerilog Event Regions, Race Avoidance & Guidelines

Understanding SystemVerilog event regions  and fundamental coding guidelines can help eliminate race conditions from SystemVerilog designs, testbenches and the interaction between the design and the enhanced SystemVerilog Hardware Verification Language (HVL).

New SystemVerilog event regions have been added to help eliminate race conditions that could occur between design modules and verification environments.

This paper details common verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in-depth explanation of SystemVerilog event regions is included to help understand how race-reduction goals have been met. Important  design & testbench coding guidelines are also included.

SystemVerilog Event Regions, Race Avoidance & Guidelines

New superfast RFIC developed by Korean Researchers

RFIC South Korea has developed a new radio frequency (RF) chip, which it has dubbed the world's fastest wireless technology, capable of sending and receiving 10 gigabits per second over the 60 Gigahertz (Ghz) waveband.

The new RF chip could be a new competitive differentiator for smartphones.

The RF chip was developed by a team from the Korea Advanced Institute of Science and Technology (KAIST), according to a report Tuesday by Yonhap.
For example, the chip can transmit a 4.7 gigabyte movie file in just 3.76 seconds, while the same file transfer would take more than 3 minutes over Wi-Fi and over 200 minutes via Bluetooth.

"It is a key new technology that can greatly increase the competitiveness of the country's smartphones. The chip can also replace various cables that existing televisions require, which means it can be used not only in smartphones but also in other mobile devices, such as cameras," said Park Cheol-soon, a KAIST professor in charge of the research, in the report.
The size of the chip has also been minimized for use in small mobile devices by needing only one antenna for transmission of both outgoing and incoming data, unlike conventional RF chips, noted the report.

FPGA design heads into the Cloud computing

From online payments and electronic banking transactions to organizing company documents and mission-critical supply chain management systems, cloud computing now plays an ever-present role in both consumer and enterprise applications. In general, cloud computing's "pay-as-you-go" elasticity – requiring little upfront investment – tends to be its main value proposition to IT departments, although security and service disruptions are potential risks that come to mind.
But what does cloud computing mean for the FPGA design engineer? How can seemingly unlimited server resources help engineers in our daily work? This article examines the benefits and potential pitfalls of cloud computing in FPGA design from a practical, day-to-day viewpoint.

Read more …

Facebook: Goodbye to DRAM and hello to McDipper

McDipper, a Facebook-built implementation of the popular memcached key-value store designed to run on flash memory rather than pricier DRAM.

Memcached, for the unfamiliar, is an open-source key-value store that caches frequently accessed data in memory so applications can access and serve it faster than if it were stored on hard disks. It’s a very popular component of many web applications stacks, including at Facebook where the company runs thousands of memcached servers to power its various applications.

But DRAM is expensive, especially when you get to Facebook’s scale, and not all applications deserve that kind of performance. So, according to a Facebook Engineering post on Wednesday, the company designed McDipper to handle “working sets that had very large footprints but moderate to low request rates. … Compared with memory, flash provides up to 20 times the capacity per server and still supports tens of thousands of operations per second.”

Facebook has deployed McDipper for a handful of these workloads, the blog states, and has “reduced the total number of deployed servers in some pools by as much as 90% while still delivering more than 90% of get responses with sub-millisecond latencies.” It has been part of Facebook’s photo infrastructure for about a year and serves 150 gigabits of data per second — or “about one library of congress (10 TB) every 10 minutes” — over Facebook’s content-delivery network.

563268_10151454322497200_149974633_n

This is the same logic that drove Facebook to undertake its cold storage engineering effort for even more infrequently accessed data, which aims to find a middle ground between the inefficiency and latency of hard disks and the high cost of flash storage. To meet that goal, the company is getting creative by considering everything from lower-performance flash to Blu-ray — pretty much anything but tape — VP of Engineering Jay Parikh told me in January.

Building a tool like McDipper is the just the tip of the iceberg, though, when it comes to managing the cost and efficiency of infrastructure at large web companies such as Facebook. On Tuesday, eBay released its Digital Service Efficiency report that lays out a methodology for assessing the effect that infrastructure (more than 52,000 servers in eBay’s case; Facebook has even more) has on larger corporate goals such as clean energy and the bottom line.

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