Featured post

Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Friday, 15 March 2013

SystemVerilog Event Regions, Race Avoidance & Guidelines

Understanding SystemVerilog event regions  and fundamental coding guidelines can help eliminate race conditions from SystemVerilog designs, testbenches and the interaction between the design and the enhanced SystemVerilog Hardware Verification Language (HVL).

New SystemVerilog event regions have been added to help eliminate race conditions that could occur between design modules and verification environments.

This paper details common verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in-depth explanation of SystemVerilog event regions is included to help understand how race-reduction goals have been met. Important  design & testbench coding guidelines are also included.

SystemVerilog Event Regions, Race Avoidance & Guidelines

No comments:

Post a comment

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.