The Std_Logic_Vector type is predefined in the Std_Logic_1164 package as a standard one-dimensional array type with each element being of the Std_Logic type.
Std_Logic_Vector is not a part of the VHDL Standard. Instead, it is defined by IEEE Std 1164
type std_logic_vector is array (natural range <>) of std_logic;
Std_Logic_Vector is an unconstrained (unbound) vector of resolved nine-value logic elements (std_logic type), which are defined in the Std_Logic_1164 package.
The Std_Logic_1164 package defines overloaded logical operators ("and", "nand", "or", "nor", "xor", and "not") for operands of the Std_logic_vector type. In addition, conversion functions from and to Bit_Vector are supported as well.
Assignment to an object of the Std_Logic_Vector type can be performed in the same way as in case of arrays, i.e. using single element assignments, concatenation, aggregates, slicesor any combination of them. Moreover, because the elements are of resolved type it is allowed to make multiple assignments to a Std_Logic_Vector object type. In such a case, the resolution function defined for Std_Logic is used.
Type T_Data is array (7 downto 0) of std_logic;
signal DataBus, Memory : T_Data;
CPU : process
variable RegA : T_Data;
DataBus <= RegA;
end process CPU;
Mem : process
DataBus <= Memory;
end process Mem;
Std_Logic_Vector is the best choice for buses, which are driven from different places, like the above listed data bus. Such a multiple assignment would be illegal if a Bit_Vector was used.
· Std_Logic_Vector should not be confused with the Std_Ulogic_Vector type. Elements of the latter are of the type Std_Ulogic and are unresloved version of Std_Logic. This means that it is illegal for the two values (e.g. '0' and 'Z') to be simultaneously driven into a signal of the Std_ulogic type.
· In order to use the Std_Logic_Vector type, the Std_Logic_1164 package must be explicitly listed at the beginning of an entity: