Procedural Assignments

Formal Definition

The procedural assignments enable updating registers.

Simplified Syntax

register_identifier = expression;

register_identifier <= expression;

Description

The procedural assignments can be used only within the structured procedures (always, initial, task, function).

The left-hand side of assignment should be one of the following:

· Register.

· Bit-select of register.

· Part-select of reg, integer, or time data type.

· Memory word.

· Concatenation of any of the above.

The Verilog HDL contains two types of procedural assignments statements: blocking (Example 1) and non-blocking (Example 2) procedural assignments.

If a current statement contains a blocking procedural assignment then the next statement will be executed after the execution of the current statement (in the next step of the simulation).

If a current statement contains a non-blocking procedural assignment then the next statement will be executed at the same time (in the same step of the simulation).

A block of statements with non-blocking procedural assignments has similar functionality as a group of statements within a fork-join block (Example 3).

Examples

Example 1

begin
  a = 1;
  #10 a = 0;
  #5 a = 4;
end

During the simulation, this block will be executed in 15 time units. At time 0 the 'a' variable will be 1, at time 10 the 'a' variable will be 0, and at time 15 (#10 + #5) the 'a' variable will be 4.

Example 2

begin
  a <= 1;
  #10 a <= 0;
  #5 a <= 4;
end

During the simulation this block will be executed in 10 time units. At time 0 the 'a' variable will be 1, at time 5 the 'a' variable will be 4, and at time 10 the 'a' variable will be 0.

Example 3

fork
  a = 1;
  #10 a = 0;
  #5 a = 4;
join

This fork-join block has the same functionality as the block with non-blocking assignments from example 2.

Important Notes

· Statements that contain the non-blocking procedural assignments are executed in the same simulation cycle.


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