**Formal Definition**

Delays specify a time in which assigned values propagate through nets or from inputs to outputs of gates.

**Simplified Syntax**

#value

#(value)

#(value, value)

#(value, value, value)

**Description**

Delays specify how values propagate through nets or gates.

The net delay declaration specifies a time needed to propagate values from drivers through the net. It can be used in continuous assignments (Example 1) and net declarations (Example 2).

The gate delay declaration specifies a time needed to propagate a signal change from the input of a gate input to its output. The gate delay declaration can be used in gate instantiations (Example 3).

The delays can be also used for delay control in procedural statements (Example 4 - see Procedural timing control for more explanations).

The delays declaration can contain up to three values: rise, fall, and turn-off delays. The default delay is zero. If only one delay value is specified then it is used for all signal changes. If two delays are specified then the first delay specifies the rise delay and the second delay specifies the fall delay. If the signal changes to high-impedance (z) or to unknown (x) then the smaller value will be used. This means that if delays are specified as follows: #(4,3) then the second value (3) will be used for signal changes to z or x value.

If three values are given, then the first value specifies the rise delay, the second specifies the fall delay, and the third specifies turn-off delay. If the signal changes to unknown (x) value, then the smallest of these three values will be used.

Value changes | Delay used for propagation if: | |||

From: | To: | 1 delay specified | 2 delays specified | 3 delays specified |

0 | 1 | d1 | d1 | d1 |

0 | x | d1 | min(d1, d2) | min(d1, d2, d3) |

0 | z | d1 | min(d1, d2) | d3 |

1 | 0 | d1 | d2 | d2 |

1 | x | d1 | min(d1, d2) | min(d1, d2, d3) |

1 | z | d1 | min(d1, d2) | d3 |

x | 0 | d1 | d2 | d2 |

x | 1 | d1 | d1 | d1 |

x | z | d1 | min(d1, d2) | d3 |

z | 0 | d1 | d2 | d2 |

z | 1 | d1 | d1 | d1 |

z | x | D1 | min(d1, d2) | min(d1, d2, d3) |

**Table 6 Rules for delays depending on number of specified values**

**Examples**

Example 1

**assign** #5 out = in1 & in2;

All value changes on *in1* or *in2* signals will propagate to out port in 5 time units.

**assign** #(1,3) b = ~a;

All value changes on signal 'a' that cause signal 'b' to change its value to '1', will propagate through net 'b' in 1 time unit. If '~a' expression equals 0 then it will take 3 time units to propagate this value through net 'b'. If the result of '~a' expression is unknown (x) or high-impedance (z) value, then it will take 1 time unit (because 1 is less than 3 therefore this value will be used for propagating these value changes).

**assign** #(5,3,7) w_or = |bus;

If result of right-side expressions is 1 then 5 will be used as the delay.

If result of right-side expressions is 0 then 3 will be used as the delay.

If result of right-side expressions is high-impedance (z) then 7 will be used as the delay.

If result of right-side expressions is unknown (x) then 3 will be used as the delay (because this is the smallest of these three values).

Example 2

**wire** #(5) ready;**tri** #(2,3) a;**wand** #(3,2,1) signal_1;

Net ready has only one delay specified.

Net a has two delays specified.

Net signal_1 has three delays specified.

Example 3

**and** #1 and_gate (o, i1, i2);**or** #(5,1) or_gate (o, i1, i2);**bufif1** #(3,4,5) buffer (o, i, c);

The *and_gate** *has one delay specified.

The *or_gate* has two delays specified.

The *buffer* has three delays specified.

Example 4

**reg** r;**initial** **begin**

#10 r = 1'b1;

r = #10 1'b0;**end**

**Important Notes**

- If fewer than 3 delays are specified then the smallest value is used for the missing delay(s).

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