Floating Point Adder and Multiplier

The FP Adder is a single-precision, IEEE-754 compliant, signed adder/substractor. It includes both single-cycle and 6-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 385 CLBs and with a theoretical maximum operating frequency of 6MHz for the single-cycle design and 87MHz for the pipelined design. The design was tested at 33MHz.

The FP Multiplier is a single-precision, IEEE-754 compliant, signed multiplier. It includes both single-cycle and 4-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 119 CLBs and with a theoretical maximum operating frequency of 8MHz for the single-cycle design and 90MHz for the pipelined design. The design was tested at 33MHz.

Features

- IEEE-754 compliant
- 32 bits, single precision
- Works with normalized and un-normalized numbers
- Simple block design, good for FP arithmetic learning
- Adder
- 385 CLBs
- 87 MHz, 6-stage pipelined
- Multiplier
- 119 CLBs
- 90 MHz, 4-stage pipelined

5 comments:

  1. i need floating point multiplier code in verilog language.. could u please send the code to my mail id.......mageshv23@gmail.com

    ReplyDelete
  2. need code of this

    ReplyDelete
  3. can u please help me with the code.
    email: visitmujtaba@gmail.com

    ReplyDelete
  4. need code of this my email id is=hirpara028@gmail.com

    ReplyDelete
  5. hello!!!!! i need verilog code for this project can u pls send that to my mail id "mounika.star.6@gmail.com"

    ReplyDelete

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