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Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Monday, 30 April 2012

Draw OR gate using 2:1 MULTIPLEXER

 

OR_by_mux

Applying similar concept of AND gate using 2:1 MULTIPLEXER, make either of input A or B as select line of MUX, connect other input to 0th input line. 1st input of the MUX is always tied to logic 1.

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