VLSI Interview Questions - 2

  • What is the frequency of the DDR / voltage
  • What is the memory size ; explain prefetch in memory context
  • What is the Bit length for data
  • Basic protocol level DDR knowledge
  • What is absolute jitter
  • What are the types of jitter you know
  • How do you make power measurements
  • Asynchronous reset flip flop / Synchronous reset flip flop difference
  • What is a asynchronous reset D flip flop
  • How do you double the clock frequency using combinational logic
  • What do you understand by synthesis
  • What is the basic difference between ASIC and FPGA design flow
  • Blocking and non-blocking statements
  • Tools used for front end
  • PCI clock frequency
  • What is metastability
  • Delay parameters which matter for DDR ( cas latency what do u know about it )
  • RAS / CAS
  • Master – Slave FF
  • Add delay on FF1-FF2 D1Q-D2 path  and analyze a circuit ( a double inverter)
  • Swap the delay onto the clock line and analyze the circuit ( double inverter )
  • Delay nos. given 20 ns (double inverter) on clock skew line, 5 ns on the first FF to second FF line ; 100 ns clock period – analyze the circuit
  • 4:1 mux from 2:1 mux ABCD in order – draw truth table and prove
  • A equality comparator design – make it an inverter
  • XOR gate from NAND gate
  • Explain DDR protocol and timing
  • Ethernet packet format
  • Test setup and explain settings
  • Two critical debug you have done in your career and lessons learnt
  • Decoder design – explain address decoder how it works given x number of rows and columns draw timing and circuit
  • 8085 block diagram ( general uP concepts)
  • DRAM
  • FF can be used in memory? Why / why not ?  FF vs DRAM
  • Five skills obtained from board design / rules – best practices
  • Latch vs FF
  • VHDL code snippet
  • SR FF.
  • DDR banks
  • 100 MHz clock is used to give input – need to send out data at 200 MHz suggest circuits for this
  • DDR explanation – chip level
  • 100 MHz in from 1 PLL clock / 100 MHz out from PLL2 clock – design circuit
  • What problems will come in case (q 20 / 22)
  • FIFO design details and problems
  • some more design problems were asked to be analyzed
  • What is set up time
  • What is hold time
  • ASIC Design flow
  • Challenges in ASIC Design
  • Latch and Flip-Flop
  • Design a simple circuit for motion detector
  • Use of a decoder
  • Types of Flip Flop
  • Which is the most common flip flop used in ASIC designs
  • FF --- Combinational Logic --- FF ( Analysis of standard circuit)
  • Analysis of circuit with delays ( buffers added to clock lines)
  • How to find the maximum clock frequency of a given circuit
  • Synthesis tools and styles
  • Timing constraints to be given for ASIC design
  • What happens when you decrease the clock frequency – does setup / hold time violations at say 300MHz frequency vanish at 3 MHz
  • What all influence the delay of an element ( Flop – capacitance ?)
  • What parameters influence delay ( temperature effect on delay)
  • If input transition is faster what happens to delay of a cell
  • What do you understand by drive strength
  • High drive of a cell – correlates to what ?
  • Importance of hold time (adder can become subtractor – Function change!!)
  • How to solve set-up time violations
  • How to solve hold time violations
  • What is PRBS
  • What is the difference between single ended and differential
  • Why is PRBS needed in a tester
  • USB protocol / packet level understanding? Basics explanation
  • 80 MHz DDR – what do you understand from this
  • SDR and DDR difference and advantages
  • Test setup
  • Triplexer – why passive optical networks what it means
  • WDM – CO – CPE
  • What do you understand by a Loopback why is it needed
  • Challenges in finding maximum clock frequency in ASIC design
  • Power estimation in chips ?
  • Why is place and route important – any understanding of the same
  • What is skew – clock skew
  • What is slew – slew rate
  • Why do you want to do verification and enter ASIC domain
  • What is jitter
  • What is cycle – cycle / period jitter. How is it estimated
  • Common i/fs in a system
  • Pulse width
  • Why is setup and hold time first needed
  • Effect of temperature on delays ( delay increases with temperature)
  • Why clock skew arises
  • What is positive and negative skew
  • Is positive skew and advantage or disadvantage – how does it help
  • What is the worst pattern that can be used to test a set of lines
  • SSN – crosstalk
  • what do you actually look for in SI
  • What do you do in a bring-up
  • What is Custom and Semi-Custom ASIC design
  • ASIC – FPGA difference ( low power is a key)
  • When a Flop is used; when a latch is used and why?
  • Why random patterns?
  • DFM?
  • Clock tree routing problems
  • Models for components
  • Buffer circuit in IOs – Pulse width distortion / duty cycle distortion why it happens performance before and after pads causes for degradation
  • Can you explain a general verification methodology flow 
  • Explain your verification architecture 
  • Why do you think we need functional coverage 
  • Can you explain e-manager coverage implementation methods you have used 
  • DDR + problems you faced in bring up 
  • Can you give me an FSM/code/circuit to implemet code for following waveform 
  • 32 bit addr / 32 bit data / size -- map to 64 bit memory - give structure / how will you sample data for byte, word, half word, dword accesses 
  • You have 256 MB sys memory - (insufficient say for ur huge ASIC) how will u verify 
  • Dynamic memory 
  • List and indexed lists 
  • Can you explain some RISC processor architecture you know 
  • RISC vs CISC you know from college 
  • How can specman handle semaphores 
  • Some addressing fundamentals
  • Multiple threads in your env - what did you implement to run three cores simultaneously. 
  • AXI - addressing ; 4k page boundary cross over fetches; wrapping concept ; Multiple slave out of order transaction support - waveforms as to how these transactions will be ; size / length concepts

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