On the face of it, this is true. VHDL was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving VHDL code from one simulator to another involves one or two minor changes to the VHDL. Two different synthesis tools may have broad agreement of what constitutes synthesizable code, but may interpret that code in different ways.
Subscribe to:
Post Comments (Atom)
Popular Posts
-
Today India is home to some of the finest semiconductor companies in the world. The semiconductor companies in India are reputed across t...
-
Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verification Methodology) is a standardized methodology for verify...
-
1. 8-bit Micro Processor 2. RISC Processor in VLDH 3. Floating Point Unit 4. LFSR - Random Number Generator 5. Versatile Counter 6. ...
-
There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “10...
-
Design 1: Design 2:
-
There are some differences between UDIMMs and RDIMMs that are important in choosing the best options for memory performance. First, let’s ta...
-
There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “...
-
Look at the truth table of AND gate. When any of the one input is zero output is always zero (or same as that input); when the other input...
-
Applying similar concept of AND gate using 2:1 MULTIPLEXER , make either of input A or B as select line of MUX, connect other input to ...
-
Q11: Difference between module & class based TB? Ans: A module is a static object present always during of the simulation. A Cl...
No comments:
Post a comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.