Featured post

Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Friday, 25 November 2011

Can I use VHDL for the analog part of a design?

Yes and No. Yes, there is a VHDL Analogue and Mixed Signal language (VHDL-AMS), based on VHDL 93, which allows modeling of both analogue and digital in the same language. However the idea of analogue synthesis is still in its early days, so currently you wouldn't normally be able to go on and synthesize an analogue model written in VHDL-AMS. There's a VHDL-AMS website at www.eda.org/vhdl-ams.

No comments:

Post a comment

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.