Verilog Module structure

Below code gives basic structure of a verilog module

module M (P1, P2, P3, P4);

input P1, P2;
output [7:0] P3;
inout P4;
reg [7:0] R1, M1[1:1024];
wire W1, W2, W3, W4;
parameter C1 = "This is a string";

initial
begin : BlockName
// Statements
end

always
begin
// Statements
end

// Continuous assignments...
assign W1 = Expression;
wire (Strong1, Weak0) [3:0] #(2,3) W2 = Expression;

// Module instances...
COMP U1 (W3, W4);
COMP U2 (.P1(W3), .P2(W4));

task T1;
input A1;
inout A2;
output A3;
begin
// Statements
end
endtask

function [7:0] F1;
input A1;
begin
// Statements
F1 = Expression;
end
endfunction

endmodule

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