Switch Level design of 2x1 Multiplexer in Verilog

Below written is a switch level coding example in verilog. Its a code for 2x1 multiplexer.

module mux2_1(q,d,select); //Declared parameter list
output q; //Outputs are declared
input[1:0]d; //Inputs are declared
input select;
wire w; //Internal nets
not(w,select); //Pre-defined gates are used
cmos c1(q,d[0],w,select);
cmos c2(q,d[1],select,w);
endmodule//End Module

enjoy coding…. !!!!