Comparison Of Intel and AMD Processors

An overview of notebook and desktop processors offered by Intel and AMD.

amdintel

What’s the big deal about choosing a processor?

The processor (also called CPU, short for Central Processing Unit) is the "engine" of a computer. It is the most important component in determining how fast or 'snappy' the system will operate across applications both now and in the near future.  Like the engine of an automobile, a processor can be fast, slow, power hungry or power efficient subject to the kind of work the computer is being considered for. It is important to round out what kind of things you will be doing on the system to best select a computer with a CPU most suitable to your needs.

Unlike other components of a notebook computer, the CPU is -- with rare exception -- a fixed component. This is in contrast to RAM and hard disk storage which can typically be upgraded. Therefore, another consideration is the fact that (important as the CPU is) the CPU you choose will be the same throughout the life of the system. This implies that as programs become more sophisticated, the computer's ability to handle such programs will be directly affected by the decision made at purchase all that time ago. This choice may mean the difference between a system that is useful for another year or two versus one that isn't -- much sooner. As a final consideration in choosing a CPU is the suggested or minimum requirements of either the programs that is planning on being run, or academic department recommendations as a guide as to the relative kind of performance required for a particular field of study.

The product line comparisons hierarchy 

Currently, the two largest manufacturers of CPUs in the world are Intel and AMD. The following provides a short profile of the companies and the current state of their products.

Intel

The current performance and market leader at the time of this writing is Intel.  Intel is currently the sole supplier of processors for all recent Apple computers (Macbook, Macbook Pro, Mini, iMac etc.) and are found in virtually all major computer manufacturer's product lineups. Intel's most current crop of CPUs are the Core iX-series processors which include the i3, i5 and i7; as of January 2011, these series of processors entered their 2nd generation (codenamed "Sandy Bridge" where the 1st generation was codenamed "Nehalem", differences explained under the special features section).  

AMD

AMD is the second largest supplier of processors for personal computers.  Many of their products are found in both high-performance and budget-oriented notebooks as well as low-cost, enthusiast-oriented desktop builds.  The Phenom II and Fusion platforms comprise AMD's most popular and mainstream offerings at the time of this writing.

Beneath, we provide a chart which compares the relative performance between competing product lines within Intel's and AMD's offerings. These are organized by the following three classes: high-end, mid-range and economy.  It is important to note that though this comparison offers a reference of relative performance within each brand, it does not necessarily indicate absolute rankings between competing Intel and AMD products (for instance, the Core i7 is in the same row and category as the Phenom II series but offers superior general performance). Further, the Core iX Mobile series only indicate relative performance for notebook platforms -- that is, it is generally not useful to compare them to desktop processors such as the Intel Core i7 or the Phenom II series.

High End Processors : Intensive Statistical Analysis, Professional Video/Audio Creation, Advanced 3D Graphics

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(2nd generation "Sandy Bridge")

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Intel Core i7

As Intel's flagship processor, the i7 is a 64-bit processor offering either 2, 4, or 6 cores of the highest levels of general performance available.  The i7 combines Hyper Threading and Turbo Boost technologies for the most demanding and advanced of applications.

Intel Core i7 Mobile

Intel's Core i7 Mobile features unparalleled performance on notebooks, incorporating significant power savings while implementing the same features as the non-mobile i7, Hyper Threading and Turbo Boost. The i7 Mobile is available on notebooks with 2 or 4 cores; currently the 4 core version offers higher performance in some respects but heat and battery life are concerns.

AMD Phenom II X6

AMD's Phenom II X6 represents the industry's first consumer class six-core processor. The X6 offers the highest levels of performance ideal for the most intensive of tasks - bolstered by AMD's new Turbo Core technology, the X6 is able to optimize performance in a variety of situations.

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(2nd generation "Sandy Bridge")

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Intel Core i5

Based upon the same architecture as the i7, the i5 is also a 64-bit processor that features 2 or 4 cores at a similar class of performance of the i7 processor at a lower cost. The i5 features Turbo Boost and Hyper-Threading technology but do not possess as much cache memory as the i7.

Intel Core i5 Mobile

The Intel Core i5 Mobile while also featuring Hyper Threading and Turbo Boost possesses a similar but lesser class of performance than the Core i7 Mobile with less cache and available in notebooks only with 2 cores. The Core i5 Mobile is a high performance processor with low energy requirements.

AMD Phenom II X4

AMD's latest generation of consumer class 4 core processors, the quad-core Phenom II X4 chips are designed to deliver performance ideal for all kinds of multimedia as well as in the most demanding of applications such as virtualization.

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(2nd generation "Sandy Bridge")

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Intel Core i3

Derived from the same architecture as the higher end i5 and i7, the i3 is available strictly as a dual core processor. Though Hyper Threading is available, it does not feature TurboBoost. The Core i3 processor presents higher levels of performance than the Core 2 at a smaller cost.

Intel Core i3 Mobile

The Intel Core i3 Mobile descends similarly from the i3, presenting a fast, 64-bit computing experience with the intelligent architecture of the i5 Mobile and i7 Mobile. The i3 Mobile features 2 cores and Hyper Threading but does not include Turbo Boost technology

AMD Phenom II X3 & X2

AMD's Phenom X3 and X2 processors boast 3 or 2 cores that offer excellent performance value; great for all around usage on a small budget all while utilizing AMD's latest architecture technology seen in the Phenom II X4 series

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Intel Core 2 Quad

The Core 2 Quad features 4 processing cores to optimize gaming, video, and image processing. Built on the same architecture as the Core 2 Duo, this processor excels on multi-tasking with performance hungry applications.

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Intel Core 2 Extreme

Available in both 2 and 4 core versions, distinguishing features of the Extreme series include higher bus speeds than the non-extreme versions, and an unlocked clock multiplier for further customization of your computing performance.

Mid Range Processors : Speed & Multi-tasking, Adobe Creative Suit, All-Around Use, Basic 3D Graphics

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Intel Core 2 Duo

Contains two processing cores to optimize gaming, video, and image processing. Laptops with this chip tend to be thinner and and more energy-efficient.

AMD Phenom I X3 & Phenom I X4

AMD's first generation of consumer class processors featuring quad and triple core performance found in desktop builds. Features 64-bit computing performance as well as AMD's HyperTransport bus technology.

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Intel Pentium Dual Core

Dual core processor based on the Core microarchitecture. A class beneath the Core 2 Duo and Core Duo of Intel's processor offerings, the Pentium Dual Core is available in current desktops and laptops.

AMD Turion II Ultra / AMD Turion II

The Turion II and Turion II Ultra are AMD's mainstream mobile processor platform; they provide excellent all-around performance for multimedia such as high definition video. As these are often paired with AMD/ATI graphics, budget configurations containing these processors are also sufficient for basic 3D graphics and gaming.

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Intel Core Duo / Intel Core Solo

The Intel Core Duo and Core Solo are dual and single core processors based on the Core microarchitecture. The Core Duo and Core Solo offers modest performance for office and limited multimedia oriented tasks.

AMD Athlon II X2

The AMD Athlon II X2 is a 2 core desktop processor that is 80% faster than it's single core counterpart. Great for multitasking and multimedia consumption on a budget.

Economy Processors : Internet Browsing, E-mail, Microsoft Office, Simple Graphics and Games

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Intel Centrino/Centrino Duo

A mobile-oriented processor based upon Pentium M or Core Duo architectures; the Centrino also integrates wireless networking technology allowing for smaller sized laptops. Offers slight performance boost over simply choosing a core duo and dell wireless card (which is typically less expensive.)

AMD Sempron

The AMD Sempron is a budget class processor seen in low cost notebooks and desktops and are considered a class above netbook/nettop processors such as the Intel Atom or the AMD Neo platforms.

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Intel Atom

Primarily found in netbooks and nettops, this processor has been designed with price and power consumption in mind. As a result, it offers much less processing power than other current Intel alternatives. This processor is available in 1 or 2 cores, with the single core option being far more prevalent.

AMD Athlon Neo / Neo X2

The Athlon Neo and Neo X2 are single and dual core processors seen in ultra-mobile platforms such as netbook and nettops. They are featured with ATI integrated graphics for reasonable multimedia playback performance.

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Intel Celeron

Intel's economy model processor. It is the most basic, and thus the slowest. It has less cache than other Intel processors, so even if it has the same Ghz rating as another processor, it will be slower. We usually do not recommend this processor because it offers the least in terms of longevity.

 

Benchmarks

This is not meant to be a comprehensive list, but rather a way to identify different branches in processors. To see a more comprehensive comparison of specific processor types, follow the benchmark links below. Benchmark websites rank processors within and between series. The highest rated processors are typically used for server applications and for simplicity, those products are omitted in the set of rankings above (eg. Intel Xeon and AMD Opteron); rather the processors that are found in desktops and notebooks are included.

It is further important to recognize that general processor speed is not solely atttributed by its frequency -- these are the Mhz and Ghz numbers often seen -- of the processor when comparing between different product lines as is the common misconception. For instance, an Intel Pentium 4 3.8 Ghz processor is slower than an Intel Core Duo or AMD Phenom. The primary reasons for this is a function of the architecture and the associated features therein (particulrly additional physical cores, advancing of bus technology, etc). It is thus, only applicable comparing frequency ratings to ascertain relative performance within exact product lines (eg. Core 2 Duo vs. Core 2 Duo). The chart beneath will give a rough idea of the hierarchy of performance expected in faring against competing product lines at the time of this writing. It may also be helpful to understand that versions of processors found in desktops tend to be higher in performance than their notebook counterparts of the same product line; this is done to maintain thermal requirements, battery life and minimize size at the cost of speed.

 

Special Features Explained

In this section, we breakdown the practical meaning of some important technical features included in the various processors available. Please not that this is not a comprehensive listing and what is described are the most common/relevant features offered.

Special Features

Explanation

Processors Using Feature

Intel Features

Hyper Threading

The operating system treats the processor as two processors instead of one. This increases the speed of the computer.

Pentium 4, Core i7, Core i5, Core i3

Turbo Boost

Allows the processor to intelligently overclock themselves so long as thermal and electrical requirements are still met.

Core i7, Core i5

Intel QuickPath Interconnect (QPI)

A new Intel technology which replaced Front Side Bus (FSB) -- similar in purpose to AMD's competing HyperTransport technology.

Implemented in some fashion in all Intel core iX series processors

Execute Disable Bit

Prevents certain viruses from infecting the system by labeling some data "executable."

Current Intel processors

vPro

Best for IT people trying to maintain several workstations. It is able to detect systems, even in powered-off states. Synchronizes remote desktop, security, and other multi-station support features. Decreases desk-side maintenance visits.

Core Duo, Core 2 Duo

ViiV technology

Intel's bundle for enhancing multimedia. Supports HD resolutions 720p up to 1080i.

Pentium D, Extreme, Core Duo, Core 2: Duo, Extreme, Quad.

AMD Features

Hyper Transport

Feature that allows for faster processing speed and better energy efficiency.

Current AMD processors

Cool'n'Quiet

Reduces heat and noise of processors allowing for increased energy efficiency.

Phenom I & II, Athlon, Sempron (with exceptions)

Turbo Core

Turbo Core allows for contextual overclocking of the processor to optimize performance subject to electrical and thermal requirements/specifications.

Phenom II X6

CoolCore

Limits unused elements of the processor such that power is conserved -- allows for increased notebook battery life on a single charge.

Phenom I & II, Turion

Dynamic Power Management

Allows for dynamic power management to optimize energy consumption while maintaining performance levels.

Phenom I & II, Turion

Xilinx’s New Virtex-7 2000T FPGA with equivalent of 20 million ASIC gates

Xilinx has announced the first shipments of its Virtex-7 2000T Field Programmable Gate Array (FPGA). The Virtex-7 2000T is the world’s highest-capacity programmable logic device – it contains 6.8 billion transistors, providing customers access to 2 million logic cells. This is equivalent to 20 million ASIC gates, which makes these devices ideal for system integration, ASIC replacement, and ASIC prototyping and emulation.
This capacity is made possible by Xilinx’s Stacked Silicon Interconnect technology – also referred to as 2.5D ICs. The simplest packaging technology is to have a single die in the package. The next step up the “complexity ladder” is to have multiple die is the same package, but for all of these die to be attached directly to the package substrate. In this case, compared to the tracks on the die, the tracks on the package substrate are relatively large, slow, and driving signals onto them consumes a lot of power.
What Xilinx are doing is to go one more step up the technology ladder to use a special layer of silicon known as a "silicon interposer" combined with Through-Silicon Vias (TSVs). In this first incarnation of the technology, four FPGA die are attached to the silicon interposer, which – in addition to connecting the FPGAs to each other – provides connections to the package as illustrated below.

xilinx-bc-00

In the case of the Virtex-7 2000T, the FPGA die are implemented at the 28 nm technology node, while the passive silicon interposer is implemented at the 65 nm technology node. Implementing the large silicon interposer at this higher node reduces costs and increases yield without significantly degrading performance.
One way to think about this is that the silicon interposer essentially adds four additional tracking layers that can be used to connect the FPGAs to each other with more than 10,000 connections between each pair of adjacent die!
On top of this, Through-Silicon Vias (TSVs) are used to pass signals through the silicon interposer to C4 bumps on the bottom of the interposer. These bumps are then used to connect the interposer to the package substrate.

A view of Xilinx’s Virtex-7 2000T device showing the
packaging substrate (bottom), silicon interposer (middle),
and four FPGA die (top).

Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, this stacked silicon interconnect technology is said to provide over 100X the die-to-die connectivity bandwidth-per-watt, at one-fifth the latency, without consuming any of the FPGAs' high-speed serial or parallel I/O resources.
Of particular interest to designers is the fact that, despite being composed of four die, the Virtex-7 2000T preserves the traditional FPGA use model in that users will program the device as one extremely large FPGA with the Xilinx tool flow and methodology.
Xilinx’s first application of 2.5D IC stacking gives customers twice the capacity of competing devices and leaps ahead of what Moore’s Law could otherwise offer in a monolithic 28-nanometer (nm) FPGA. Xilinx says that its customers can use Virtex-7 2000T FPGAs to replace large capacity ASICs to achieve overall comparable total costs in a third of the time, creating integrated systems that increase system bandwidth and reduce power by eliminating I/O interconnect, and accelerating the prototyping and emulation of advanced ASIC systems.

xilinx-bc-02A top and bottom view of Xilinx’s Virtex-7 2000T
device,
the world’s highest-capacity FPGA using
Stacked Silicon Interconnect technology.

“The Virtex-7 2000T FPGA marks a major milestone in Xilinx’s history of innovation and industry collaboration,” said Victor Peng, Xilinx Senior Vice President, Programmable Platforms Development. “Of significance to our customers is the fact that Stacked Silicon Interconnect technology offers capacities that otherwise wouldn’t be possible in an FPGA for at least another process generation. They can immediately add new functionality to existing designs while forgoing an ASIC, cost reduce a 3 or 5 FPGA solution into a single FPGA or move ahead with prototyping and building system emulators using our largest FPGAs at least a year earlier than typical for a new generation.”
Historically, the largest devices that make up an FPGA family are the last to be made available to customers.  This is a result of the time it takes a new semiconductor process to ramp up and support the yields per wafer that make the largest devices economically viable. Xilinx’s Stacked Silicon Interconnect technology overcomes the challenges of yielding defect-free, large monolithic die by building the world’s largest capacity programmable logic device from four separate FPGA die interconnected upon a passive silicon interposer.
“ARM is pleased to work with Xilinx in deploying the class-leading Virtex-7 2000T device into our validation infrastructure,” said John Goodenough, Vice President Design Technology and Automation, ARM. “The new device underpins a flexible, yet targeted, emulation architecture and delivers a significant capacity improvement, allowing us to more easily run complete system verification and validation for our next generation processors.”
The Virtex-7 2000T device also provides equipment manufacturers with an integration platform that will help them overcome the challenges of lowering power while increasing performance and capabilities. By eliminating the I/O interfaces between different ICs on a circuit board, a system’s overall power consumption can be reduced considerably.
Consider the following example provided by Xilinx that compares a single Virtex-7 2000T with four of the largest monolithic ICs as illustrated below:

 

xilinx-bc-00b

Actually, this is not really a fair comparison, because in terms of capacity the Virtex-7 2000T is equivalent to only around two of the largest monolithic ICs. But even comparing to two monolithic ICs results in a significant power advantage. (Having said this, I’d be interested to know just what was being exercised in this example – Logic? Memory? DSP slices? SERDES channels? – and at what frequency.)
Customers can also lower bill-of-material, test and development cycle costs when fewer IC devices are required on a circuit board. Because the die align side by side on a silicon interposer, this technology avoids the power and reliability issues that can result from stacking multiple dies on top of each other.  As was previously noted, the interposer includes over 10,000 high speed interconnects between each die enabling the high-performance integration required for a wide range of applications.
The Virtex-7 2000T FPGA gives customers the capacity, performance and power typically only found in large capacity ASICs, with the added benefits of re-programmability. In addition to having 1,954,560 logic cells, the Virtex-7 2000T device includes configurable logic blocks totaling 305,400 CLB slices and max distributed RAM of 21,550 Kbits. It has 2,160 DSP slices, 1,292 x 36Kb BRAMs (giving a total of 46,512 Kb of BRAM), 24 clock management tiles, four PCIe blocks and 36 GTX transceivers (each capable of 12.5 Gbits/second). It also has 24 I/O banks and a total of 1,200 user I/Os.
For the growing number of systems and markets where economics work against ASIC development, the Virtex-7 2000T FPGA offers a unique, scalable alternative to the risk of re-spins and more than $50 million in non-reoccurring engineering (NRE) costs of a 28nm custom-made IC.
All Xilinx 28nm devices – Artix-7, Kintex-7, Virtex-7 FPGAs, and the Zynq-7000 EPP – share a unified architecture that supports design and IP reuse within and across families. They are all built on TSMC’s 28nm HPL (low power with HKMG) process to deliver FPGAs that consume 50 percent less static power than competing devices. Because lower static power becomes increasingly important as device capacity goes up, 28nm HPL is a key factor behind the Virtex-7 2000T device’s lower power consumption compared to designs implemented in multiple FPGAs.

Xilinx Shatters Record with World's Highest Capacity FPGA: Virtex-7 2000T

The Virtex®-7 2000T FPGA is the first device to use 2.5-D IC stacked silicon interconnect technology to deliver "More than Moore" capacity: 2 million logic cells, 6.8 billion transistors - 2x the capacity of the largest competing device.

World’s Highest Capacity FPGA - Now Shipping

The Virtex®-7 2000T FPGA delivers greater than 2X the capacity and bandwidth offered by the largest monolithic devices while delivering the time-to-volume advantages of smaller die. Utilizing innovative 2.5D Stacked Silicon Interconnect (SSI) technology, the Virtex-7 2000T FPGA integrates 2 million logic cells, 6.8 billion transistors and 12.5Gb/s serial transceivers on a single device making it the world’s highest capacity FPGA offering unprecedented system integration in addition to ASIC prototyping and ASIC replacement capabilities.

Industry's Highest System Performance

Virtex-7 FPGAs are optimized for advanced systems requiring the highest performance and highest bandwidth connectivity. The Virtex-7 family is one of three product families built on a common 28nm architecture designed for maximum power efficiency and delivers 2X higher system performance at 50% lower power than previous generation FPGAs.

The Virtex-7 family consists of T, XT and HT devices to meet a wide array of market requirements:

Virtex-7 T devices deliver unprecedented levels of capacity and performance enabling ASIC prototyping, emulation and replacement

  • Up to 2M logic cells, 6.8 billion transistors and 12.5Gb/s serial transceivers on a single device
  • Enables non-linear integration to reduce board space, lower power and increase system performance
  • Delivers highest bandwidth, lowest latency by eliminating multiple chip bottlenecks
  • Enables rapid development and emulation of advance node ASICs

Virtex-7 XT devices offer the highest processing bandwidth with high performance transceivers, DSP and BRAM

  • Integrates up to 96 10G Base KR  backplane capable  serial transceivers
  • 5.3 TMACs of DSP 
  • 67 Mbits of internal memory
  • >1M logic cells

Virtex-7 HT devices with integrated 28Gbps serial transceivers offer an unprecedented 2.8Tb/s of serial bandwidth

  • Up to 16 x 28 Gb/s serial transceivers for ultra-high bandwidth applications
  • Optimized for next-generation 100G, nx100G and 400G line cards with CFP2 optical interfaces
  • Superior jitter performance to exceed CEI 28G specifications

EasyPath™-7 devices offer a conversion-free path to volume production.

Unified Architecture Enables Scalability and Increases Productivity

Fabricated on a high-performance, low-power (HPL) 28nm process, all 7 series FPGAs share a unified architecture. This innovation enables design migration across the Artix™-7, Kintex™-7, and Virtex-7 families. System manufacturers can easily scale successful designs to address adjacent markets requiring reduced cost and power or increased performance and capability. The adoption of AMBA 4, AXI4 specification as part of the interconnect strategy supporting Plug-and-Play FPGA design further improves productivity with IP reuse, portability, and predictability.

Virtex-7 FPGA Key Capabilities

Maximum Capability

Virtex-7 T Devices

Virtex-7 XT Devices

Virtex-7 HT Devices

Logic density (Logic Cells)

1,955K

1,139K

864K

Peak transceiver speed

12.5Gb/s
(GTX)

13.1Gb/s
(GTH)

28.05Gb/s
(GTZ)

Transceivers

36

96

88

Peak bi-directional serial bandwidth

0.900 Tb/s

2.515Tb/s

2.784Tb/s

DSP throughput (symmetric filter)

2,756 GMACS

5,314 GMACS

5,053 GMACS

Block RAM

46.5Mb

85.0Mb

64.4Mb

PCI Express® interface

Gen2x8

Gen3x8

Gen3x8

I/O pins

1,200

1,100

700

System Solutions Enabled by Virtex-7 FPGAs

Delivering the highest bandwidth with the lowest power, Virtex-7 FPGAs address the insatiable demand for networking infrastructure bandwidth. Delivering up to 2.8Tb/s serial bandwidth, these devices enable communications equipment manufacturers to increase network capacity with next-generation hardware that operates within existing power and cooling footprints.

See How Virtex-7 FPGAs Will Benefit Your Next Design

Application

Description

ASIC Prototyping

Build a highly integrated ASIC prototyping solution with the Virtex-7 2000T. With its high logic and processing capacity, mitigate development risks for large ASIC and ASSP designs.

2x100G OTU4 Transponder/Line Card

Build a 2x100G OTU4 Transponder/Line Card using the only 28nm FPGAs that enable designers to integrate two 100G interfaces into a single FPGA for reduced board space, power, and cost.

10GPON/10GEPON OLT Line Card

Meet aggressive 10G port count integration and cost targets for Passive Optical Network (PON) Optical Line Terminal (OLT) Line Cards that bring high-speed networking to the neighborhood/home.

100GE Line Card

Virtex-7 FPGAs offer the right mix of I/O, memory and logic to enable a single-FPGA implementation of new line cards that deliver increased bandwidth.

100G OTN Muxponder

Virtex-7 FPGA XT devices enable a flexible, single-FPGA, 100G OTN Multiplexing Transponder implementation.

300G Interlaken Bridge

Create a 300G Interlaken Bridge that enables infrastructure scaling with devices that deliver up to 1.9Tbps bandwidth for bridging between MAC-NPU, NPU-Switch, NPU-TCAM using the Interlaken industry standard.

400G Line Card

Be first to market with 400GE Line Cards by designing with the only FPGAs to support 400G serial interfaces with next-generation optics.

Portable RADAR Systems

Enable high performance RADAR systems through low power, multi-channel signal recovery and processing.

Terabit Switch Fabric

Virtex-7 FPGA XT device capabilities enable Terabit Switch Fabric to support proliferating 40G/100G ports in networking infrastructure.

Key Documents

Name

Modified

Size

7 Series FPGAs Overview

09/13/2011

563 KB

7 Series Product Brief

   

WP385 - Industry’s Highest Bandwidth FPGA Enables World’s First Single-FPGA Solution for 400G Communications Line Cards

11/22/2010

623 KB

WP312 - Xilinx Next Generation 28 nm FPGA Technology Overview

03/26/2011

614 KB

WP389 - Lowering Power at 28 nm with Xilinx 7 Series FPGAs

06/13/2011

1.13 MB

WP380 - Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency

10/21/2011

2.31 MB

WP373 - Xilinx Redefines Power, Performance, and Design Productivity with Three Innovative 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices

10/11/2011

301 KB

Source : http://www.xilinx.com/

Intel to Sell Ivy Bridge Late in Q4 2011

CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun, which is a rather significant achievement as there have been apparently no major hiccups in the implementation of its 3D transistor technology. There has always been the question how Intel defines "volume", but vice president Mooly Eden told me years ago that Intel would only consider a production process volume production if it affects "millions" of processors.

Intel also stated that Ivy bridge is on target for a late Q4 "qualification for sale", which means that Intel will be begin shipping final products to its customers in the second half of the quarter. This will allow Intel to maintain its tick-tock cadence and keep the claim that a production shrink has been introduced in yet another uneven year (and so that it can state that its 22 nm chips were released in 2011). Of course, that does not mean that you will be able to buy those chips in 2011. According to Otellini, first Ivy Bridge systems should become available in Spring 2012. As Ivy Bridge is introduced and ramping up, Intel expects that its profit margins will improve as well.

Sandy Bridge has, despite an initial hiccup, worked out well for Intel. The company is on track to report $55 billion of revenue for 2011, up more than $11 billion over 2010.

Intel's Ivy Bridge Platform Enters Volume Manufacturing Ahead of Spring 2012 Product Launches

As noted by Tom's Hardware, Intel announced during its earnings conference call this week that its Ivy Bridge platform has entered volume production, with the company expecting to begin deliveries to computer manufacturers by the second half of this quarter. It will, however, take some time for Ivy Bridge to make its way into shipping products, with Intel's partners shooting for a Spring 2012 debut.

“CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun, which is a rather significant achievement as there have been apparently no major hiccups in the implementation of its 3D transistor technology. There has always been the question how Intel defines "volume", but vice president Mooly Eden told me years ago that Intel would only consider a production process volume production if it affects "millions" of processors.”

Intel had previously outlined its Ivy Bridge roadmap as targeting a launch for the first half of 2012, and so the latest news confirming that the company is on track with its new 3-D transistor technology bodes well for an on-time launch.
Ivy Bridge will offer a number of benefits for Apple's notebook lines, opening up the door to quad-core processors in the 13-inch MacBook Pro and bringing significantly faster graphicsand new OpenCL capabilities to the MacBook Air. Ivy Bridge will also support ultra high resolution displays and Intel has committed to Thunderbolt support alongside USB 3.0 in the platform.
A minor refresh to Apple's MacBook Pro line is expected any time now, with the update set to carry the line through until Ivy Bridge is ready.

Switch Level design of 2x1 Multiplexer in Verilog

cmos_2x1_muxBelow written is a switch level coding example in verilog. Its a code for 2x1 multiplexer.

module mux2_1(q,d,select); //Declared parameter list
output q; //Outputs are declared
input[1:0]d; //Inputs are declared
input select;
wire w; //Internal nets
not(w,select); //Pre-defined gates are used
cmos c1(q,d[0],w,select);
cmos c2(q,d[1],select,w);
endmodule//End Module

enjoy coding…. !!!!

Verilog Module structure

Below code gives basic structure of a verilog module

module M (P1, P2, P3, P4);

input P1, P2;
output [7:0] P3;
inout P4;
reg [7:0] R1, M1[1:1024];
wire W1, W2, W3, W4;
parameter C1 = "This is a string";

initial
begin : BlockName
// Statements
end

always
begin
// Statements
end

// Continuous assignments...
assign W1 = Expression;
wire (Strong1, Weak0) [3:0] #(2,3) W2 = Expression;

// Module instances...
COMP U1 (W3, W4);
COMP U2 (.P1(W3), .P2(W4));

task T1;
input A1;
inout A2;
output A3;
begin
// Statements
end
endtask

function [7:0] F1;
input A1;
begin
// Statements
F1 = Expression;
end
endfunction

endmodule

Johnson Counter

The Johnson counter, also called the twisted ring counter, is a variation of the ring counter, with the inverse output of the most significant flip-flop passed to the input of the least significant flip-flop. The sequence followed begins with all 0's in the register. The final 0 will cause 1's to be shifted into the register from the left-hand side when clock pulses are applied. When the first 1 reaches the most significant flip-flop, 0's will be inserted into the first flip-flop because of the cross-coupling between the output and the input of the counter.

johnson_counter_truth_table

8_bit_johnson_counter

Links:

Ring counter

A ring counter is a circular shift register with only one flip-flop being set at any particular time; all others are cleared. The single bit is shifted from one flip-flop to the other to produce the sequence of timing signals.

ring_counter_statemachine

8_bit_ring_counter

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BCD Counter

A BCD counter counts in binary-coded decimal from 0000 to 1001 and back to 0000. Because of the return to 0 after a count of 9, a BCD counter does not have a regular pattern as in a straight binary count.

bcd_counter

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Loadable Counters

Instead of counting from 0, a counter can be made to count from a given initial value. This type of counter is called a loadable counter.

loadable_4bit_synchronous_counter

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How are counters made?

Counters are generally made up of flip-flops and logic gates. Like flip-flops, counters can retain an output state after the input condition which brought about that state has been removed. Consequently, digital counters are classified as sequential circuits. While a flip-flop can occupy one of only two possible sattes, a counter can have many more than two states. In the case of a counter, the value of a state is expressed as a multidigit binary number, whose `1's and `0's are usually derived from the outputs of internal flip-flops that make up the counter. The number of states a counter may have is limited only by the amount of electronic hardware that is available. The main types of flip-flops used are J-K flip-flops or T flip-flops, which are J-K flip-flops with both J and K inputs tied together. Before that, here's a quick reminder of how a J-K flip-flop works:

J input K input Output, Q
0 0 Q
0 1 0
1 0 1
1 1 not Q

T flip-flops are used because set/reset ([1,0] [0,1]) functions are seldom used. Only the "do nothing" and toggle ([0,0] [1,1]) functions are used. Logic gates are used to decide when to toggle which outputs. Below is an example of a synchronous binary counter, implemented using J-K flip-flops and AND gates.

synchronous_4bit_binary_counter

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Intel Drops MeeGo Mobile OS, Backs Tizen Against Android

N900-MeeGo Linux Foundation and Limo Foundation are rebooting their efforts to compete with Apple and the Android camp by merging MeeGo and Limo into a new operating system called Tizen, with the backing of Intel and Samsung.

Tizen will be a Web-centric operating system for smartphones, tablets, smart TVs, netbooks and in-vehicle infotainment systems. The Linux Foundation will host the project, and plans an initial release in the first quarter of 2012, enabling the first devices to come to market in mid-2012, it said.

The goal is to develop an OS that makes it easy to a run and develop browser-based applications, where most mobile OSes today focus on running applications natively on the phone.

The future belongs to such HTML5-based applications, Imad Sousou, director of Intel's Open Source Technology Center, said in a blog post on the MeeGo website.

HTML5 will play key role in the new operating system -- and it's the reason why a new operating system is needed, rather than an upgrade to an existing one, according to Sousou: "Shifting to HTML5 doesn't just mean slapping a web runtime on an existing Linux, even one aimed at mobile, as MeeGo has been. Emphasizing HTML5 means that APIs not visible to HTML5 programmers need not be as rigid, and can evolve with platform technology and can vary by market segment," Sousou wrote.

In addition to HTML5, Tizen will have integrated support for the Wholesale Applications Community (WAC) web development environment, an operator-backed initiative to develop Web-based, cross-platform applications. WAC wants to let people use one platform to develop and distribute Web-based mobile applications that can run on a multitude of phones, and allow operators to get a piece of the app store boom. Applications based on WAC are distributed and sold via carrier-operated stores.

Over the next couple of months, Intel will be working very hard to make sure that users of MeeGo can easily transition to Tizen, Sousou said, adding that he will be working even harder to make sure that developers of MeeGo can also transition to Tizen.

Since Nokia decided in February to choose Windows Phone over MeeGo, Intel has been without a major hardware partner, but with Tizen it has Samsung on its side. Intel and Samsung will lead the Tizen technical steering team, according to a blog post on the new Tizen website.

With Android backer Google in the process of acquiring its own phone manufacturer, Motorola Mobility, and Nokia forming a close partnership with Microsoft, Samsung has been put in a position where it feels it has to look for alternatives alongside its own operating system, Bada, according to Pete Cunningham, analyst at Canalys.

But challenging Apple and the Android camp, as well as Windows Phone and Research In Motion, seems to be an almost impossible task. So far, Linux-based projects such as MeeGo and Limo have failed to make their mark, and many think this time will be no different.

"Samsung and Intel create alternative to Android. Really, another fork? This'll end well...," analyst Rob Enderle wrote on Twitter.

Cunningham agrees: "Frankly, Limo has been around for years and achieved nothing. MeeGo has shown promise, but has been slow moving. If you look at that there isn't a lot of hope for [Tizen], but it would be foolish to write off any platform coming to market," he said.

25th International conference on VLSI Design to bring back VLSI Industry into Spotlight

Conf on VLSI Design 2012 One of the key features of this Silver Jubilee conference is the ‘Student Project Contest’ of ‘Students Forum’ in which over 1000 students are expected to participate.

The 25th International conference on VLSI Design and 11th International Conference on Embedded Systems will be held at HICC, Hyderabad from January 7-11, 2012. This Silver Jubilee conference expects to bring back the spotlight to Hyderabad that hosts the finest multinational players in VLSI Design and Embedded Systems.

One of the key features of this Silver Jubilee conference is the ‘Student Project Contest’ of ‘Students Forum’ in which over 1000 students are expected to participate. ‘Students Forum’ helps the students know their career pathways and understand the technological trends in the industry. Attractive prizes will be given to the winners of the Student Project Contest. The competition is open to all BTech Grads including final year students. The last day for submission of papers is November 1, 2011.

“Participating students can benefit immensely from this silver jubilee conference,” Dasaradha Gude, Silver Jubilee Conference Convenor of 25th International VLSI Conference and 11th Embedded Systems conference, said. ‘The conference will enable them to meet with industry stalwarts, know the emerging trends in the sector and get clarity in new career opportunities. The ‘Student Paper Project’ Competition will allow the students to showcase their design skills and gain feedback from internationally acknowledged experts in the field.’

The conference also offers a big fellowship programme to support faculty & researchers who are not in a position to arrange for their own funds to attend the conference.

The 5 daylong conferences is expected to attract more than 2000 participants and will cover 2 days tutorial sessions followed by three days of regular paper sessions, special sessions, and embedded tutorials. A Reliability Aware System Design & Test (RASDAT) workshop will also be held. Industry presentation sessions, panel discussions, design contest, student project contest and industrial exhibits round off the program.

This is the third time that Hyderabad will be hosting the International VLSI Design and Embedded Systems Conference in a short span of 5 years. This indicates the strength and vitality of the VLSI & Embedded Systems Industry in Hyderabad.

“The VLSI Industry plays a crucial role in building the Technology Ecosystem and is a great catalyst in creating jobs especially in the software and application development sector” Gude said. Every chip rolled out from the industry brings new jobs for the software, programmers and application development engineers.’ He said Hyderabad is already in the world map with its engineers creating new chip for apple and also developing the first fusion chip.”

“The demand for VLSI Design and Embedded Systems talent has almost doubled over the last few years in the city with the requirement touching from the present level of  2000 to 4000.” JA Chowdary, Silver Jubilee Special Chair, JA Chowdary said while addressing the media in Hyderabad today.

This joint global level conference is a forum for researchers and designers to present and discuss various aspects of VLSI Design (Front-end & Back-end), Electronic Design Automation (EDA), Embedded Systems, and Enabling Technologies. It covers the entire spectrum of activities in the two vital areas of very large scale integration (VLSI) and Embedded Systems, which underpin the semiconductor industry.

“we expect this silver jubilee conference to bring back the spotlight to Hyderabad’s VLSI Design and Embedded System sector advancement. Our focus this year is on Embedded Solutions for Emerging Markets - Consumer, Energy and Automotive. This is a premier global level annual event that provides a platform for Students, Industry Leaders and Design Experts to discuss the growth strategies in the context of VLSI Design and Embedded Systems both in the region and globally.” Gude added

The Silver Jubilee Conference Special Chair, JA Chowdary in his comments said “The industry faces different complex issues when looking at new opportunity to grow globally both in product design and development as each country poses different challenges. We expect this year’s event will offer great networking and knowledge sharing opportunity not only for industry leaders but also for students, researchers and academicians.”

Keynote addresses by veterans in the industry will highlight the VLSI Design and Embedded Systems Conference. The conference featuring speakers from both design and technology field will give penetrating speeches to all the audience. More details of the conference program session will be released in January, 2012.

The conference is proud to create an annual platform for technical exchanges by experts from all over the world on the advancements in semiconductor research, development, and manufacturing.

Dr. Vishwani Agrawal is the Steering Committee Chair. Mr. J. A. Chowdary is the Silver Jubilee Special Chair. Mr. Dasaradha R Gude is the Silver Jubilee Conference Convener. Mr.Srimat Chakradhar is the General Chair of this Silver Jubilee Conference.

The 2011 Conference successfully attracted about 1000 attendees with a very high-quality program featuring three keynote speeches, two special sessions, invited talks, technical sessions with technical papers presented, and two short courses. Both the contributing and invited papers are of high quality, and are presented by industrial and academic leaders and students from over 10 countries.

Source : India Infoline News Service / 10:39 , Sep 29, 2011

VLSI sector faces acute shortage of engineers

HYDERABAD, SEPT. 27.2011: 

Severe shortage of VLSI (Very Large Scale Integration) engineers threatens to deter multinational companies in semiconductor industry to enter India.

“The country could generate 2,000-3,000 VLSI engineers in the last 10 years, whereas the country needs about 10,000 engineers,” said Mr Dasaradha R. Gude, Chairman of SoCtronics Technologies Private Ltd.

Addressing a press conference here on Tuesday, Mr J.A. Chowdary, Chairman of TalentSprint and former Managing Director of NVDIA India, said that acute shortage had resulted in high levels of attrition. “Unless we do something about this, MNCs working in VLSI may shy away from investing in India. Within a short span of time, India could made strides in this area. If we do not act now to improve quality in engineers, we may be killing a golden goose,” he felt.

Besides lack of knowledge in this stream in engineering colleges, costs involved to set up facilities to teach students in VLSI too became an impediment. “It costs Rs 20 lakh to buy software per computer. In India, there is no industry funding of colleges unlike in the West,” Mr Dasaradha said.

Mr Manohar Bommena, Site Leader (Hyderabad) of AMD, said that Hyderabad emerged as a leading player with over 30-40 prominent companies setting up their bases. He, however, felt that it needed a robust ecosystem and industry-academia interaction to address the issue of quality manpower.

INTERNATIONAL MEET:

Prof. Subbarangaiah K, Director of VEDA (VLSI Engineering and Design Automation), said the industry would hold 25th international VLSI Design and 11th Embedded Systems conferences in Hyderabad during January 7 to 11, in Hyderabad.

The conferences would see experts present and discuss VLSI designs, EDA (Electronic Design Automation), embedded systems and enabling technologies.

It would also have a competition for students where their project ideas would be evaluated for prizes.

Source : Business Line

Xilinx Releases Pocket Power Estimator App for the iPhone

Designers who rely on their iPhones as much as their PCs now have a quick and easy way to determine the power consumption of Xilinx's 28nm 7 series Field Programmable Gate Arrays (FPGA). The new Pocket Power Estimator (PPE) application for Apple's iPhone enables designers to see how Xilinx's 28nm programmable platforms stack up to alternatives in delivering the lowest power consumption for their systems. Designers can download the PPE from the Apple App Store today and, for the first time ever, quickly and easily explore what-if-scenarios and get immediate feedback on the estimated power consumption compared to alternatives. For more complex and detailed power analyses, designers can use the ISE® Design Suite's XPower Estimator (XPE) and the XPower Analyzer (XPA) tools.

"Manufacturers of electronic systems across all our market segments are eager to either lower their current power budgets or drive higher system performance within the same power budgets," said Xilinx Distinguished Engineer and resident power 'guru' Matt Klein. "Offering the Power Pocket Estimator (PPE) on one of the most popular smartphone platforms puts power estimation in the hands of busy designers who routinely turn to their iPhone to access information, further enhancing their design productivity."

The PPE app, which can also be used with the iPad, offers an easy-to-use GUI for the quick entering of resource requirements - such as SerDes utilization, DSP, memory, logic capacity and more. Compared to the previous generation 40nm FPGAs, Xilinx 7 series FPGAs deliver about 50 percent lower total power, on average, thanks in part to the HPL (high-performance/low-power) process technology offered by foundry partner TSMC. Further components of the power envelope that drive this total power reduction include 65 percent lower maximum (worst case) static power, 25 percent lower dynamic power, 30 percent lower I/O power, and 60 percent lower transceiver power. The PPE app takes into account these aspects of total power consumption to enable designers to easily obtain a high-level estimate of power usage by functional block, and how it compares to other Xilinx or competing devices. The PPE also includes application reference examples that designers can use as starting points to customize to their own specifications. The first release of the app includes design examples for the wired and wireless communications markets, while future releases will have additional market segment examples and support other Smartphone platforms.

7 Series Low Power Benefits:

The 28 HPL process technology avoids many yield and leakage issues seen with the embedded SiGe process used in the 28nm HP process and delivers a more cost-effective process solution. The 7 series' larger design headroom, resulting in greater voltage headroom enabled by the HPL process, allows the choice of operating voltages at a wider range of values and enables a flexible power/performance strategy. This enables Xilinx to offer the new low power -2L option for every 7 series device, providing mid-speed-grade performance at 45 percent lower static power compared to the commercial offering. The same -2L device can also function at 0.9V core voltage to provide lower power benefit, including 55 percent lower static power and 20 percent lower dynamic power compared the equivalent commercial speed grade offering.

On the design tool side of power optimization, Xilinx introduced the first automated, fine-grained clock-gating solution for FPGAs that can reduce dynamic power by up to 30 percent. This automated capability links to the place and route portion of the standard FPGA design flow and uses a set of innovative algorithms to perform an analysis on all portions of the design to create fine-grain clock-gating or logic-gating signals that neutralize superfluous switching activity. The power benefit of the intelligent clock gating can easily be realized in the PPE app by using the power optimization option. Furthermore, it is important to estimate the power consumption under worst-case conditions. The Xilinx PPE app is designed to provide the estimated total power under max conditions to provide a reasonable and realistic estimate for the respective design scenario.

Availability:

The Xilinx PPE mobile application is free of charge and is available now on the Apple App Store. A version of PPE for Android and other Smartphone platforms will be introduced later this year. To learn more about Xilinx's lower power advantage, view the YouTube video, and link to the PPE App, please visit http://www.xilinx.com/power .

About Xilinx:

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit http://www.xilinx.com/.

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