Dynamic timing analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations. The problem is that the simulations vector not can guarantee 100% coverage. The goal for the dynamic analysis is to get a 100% coverage. Dynamic timing simulation is still preferred for non-synchronous logic style. As a rule, however, only dynamic timing verification tools support glitch detection and race conditions, since these are inherently dynamic events.
Static timing analysis on the other hand check all path in the circuit even the false paths. False paths are paths that are not possible or interesting in actual operation of the circuit. Therefore you can say that static analysis starts above 100% and works towards 100% by detecting and excluding the false paths. Static tools have made major advancements in recent years, in fact all synthesis tools use static timing analysis internally. Something good about this approach is that almost all tools using it supports multi-cycle paths, in which a path delay constraint exceeds a single clock period. Everything isn't just good, many static timing tools have problems with feedback loops.