Intel’s Medfield-based Android Smartphone and Tablet

intelmedfieldphone-lg3 Intel is coming to mobile phones! Really! The chipmaker is gearing up to show off its Medfield processors at CES this year, which would be exciting if I hadn't heard this same tale way too many times before.

Intel is the company that cries wolf in mobile. Back in 2006, Intel made the mistake of ditching its Xscale line, the processors used in many early smartphones and successful PDAs. Under the questionable guidance of Marvell, Xscale then went from a dominant mobile brand to just one among many chip lines out there.

That left Intel with absolutely zero access to mobile devices. Ever since then, the company's been trying to get back into the game. But rather than enhance industry-standard ARM designs, Intel's been trying to sell everyone on x86-based chips.

Intel appears one step closer to finally breaking into the mobile arena after making their reference tablet and smartphone designs accessible to MITs Technology Review. Both devices are based around Intel’s Medfield iteration of their Atom processor, a chip based on the 32nm manufacturing process and promising better battery life than previous mobile CPUs from the silicon maker.

The Medfield-based reference smartphone was reportedly up to snuff with other currently available handset designs, boasting “Blu-ray0quality” video and the ability to shoot burst photos at 15 frames per second. The handset made available was running Android 2.3, but the tablet featured Android 4.0. Google and Intel have talked about working more closely with the development of the latest version of Android, and it could pay off as the reference tablet was said to be both as thing and as lightweight as the iPad 2 while outperforming the current generation of Android 3.0 slates.

Intel still has some work to do in integrating 3G and 4G components into the Medfield design, but the company looks to make a push over the next year or two to establish itself as a leader in the mobile market. Companies such as Qualcomm and NVIDIA currently have a leg up, but if Intel’s design proves as powerful as initial reports the battle could be starting to heat up.

Nobody's listened so far. Here are some highlights of Intel's failed push into mobile:

June 2006: Intel sells off Xscale, which had won a 2004 PCMag Technical Excellence award for heralding a new era of multimedia smartphones. Xscale was used in successful products like HP's iPAQs, Motorola's Q series, the Dell Axim and the Palm Treo. According to The Register, Intel wanted to push x86-based chips into smartphones rather than sticking with ARM designs. 

September 2007: At that year's Intel Developer Forum, Intel says it has two new chips designed for devices with 4-inch screens. Menlow and Moorestown make it into exactly zero popular handheld devices over the next few years. 

March 2008: Intel introduces the Atom processor, saying it will power "MIDs," or handheld, mobile Internet devices. Over the next year many companies introduce MIDs, but nobody buys any of them. Rather than being a power-guzzling mobile chipset, the Atom finds success in the netbook realm as a slow but power-efficient laptop chipset.

August 2008: Intel introduces the CE 3100, its first system-on-a-chip for consumer electronics. The CE 3100 generates several smart TV announcements but fewer actual sales of smart TVs.

February 2009: Intel brings a "MID bar" to Mobile World Congress. In Hebrew, "midbar" means "wilderness," as in "forty years wandering in the." Intel also announces an alliance with LG to produce more MIDs nobody wants.

January 2010: Intel says the second-generation Atom, called Moorestown, will be a real mobile chipset. Intel introduces the first phone based on the Atom Moorestown processor, the LG GW990. It is about the size and shape of a brick. It never appears in any large market. However, Intel keeps talking up Moorestown throughout 2010.

February 2010: Intel joins with Nokia to promote MeeGo, a new Linux-based OS that's the merger of Intel's Moblin and Nokia's Maemo. MeeGo is a stunning failure; Intel abandoned the project in September 2011.

January 2011: Intel CEO Paul Otellini says Windows 8 will run on smartphones with Intel chips. Other than one Steve Ballmer misquote last November, Microsoft has held a party line since then that Windows 8 will run on tablets and PCs, but not phones.

February 2011: MeeGo and Moorestown don't impress the market. Let's try again! Intel says its "Medfield" system-on-a-chip designs will come in 2012. Not much comes of Intel's mobile strategy in 2011 as the company gears up for Medfield, which will be shown at CES 2012.

March 2011: The head of Intel's ultra-mobile division leaves the company.

December 2011: Intel restructures its mobile division in an attempt to gain some traction.

To recap: fail, fail, fail, fail, fail. Faily fail fail.

Why Intel Might Succeed

There are a few new factors which might improve Intel's chances this time around. Back in September, Google said it would optimize Android for the next generation of Intel processors. That gives Intel a better OS than the proprietary Moblin/MeeGo nonsense it was working with before.

Windows 8 is also on the horizon, and while Windows 8 will work on ARM processors - a major threat to Intel - it means there will be a major tablet-oriented OS where the vast majority of legacy apps will be Intel-optimized. That could sway tablet developers to work with Intel chips.

In the phone world, though, the massive ecosystem around ARM means that Intel's sales pitch will have to be very compelling. The mobile-phone chip world is much more competitive than the desktop world Intel is used to. Within the ARM ecosystem alone, TI, Qualcomm, Nvidia, ST-Ericsson, Rockchip and others are constantly fighting for dominance. And mobile phone makers who want to try new architectures can also turn to MIPS or Power.

Intel has for years coasted on its critical mass in the PC industry. Even Apple came over to Intel after many years because of its low cost and economies of scale. But Intel doesn't have that advantage over companies like TI and Qualcomm in mobile.

It's not just about matching ARM-based designs on speed and power consumption, either. Intel will have to provide significantly better performance or lower power consumption to pull manufacturers away from the default, ARM world. Intel says it can do that by using a 32-nanometer process to produce its new system-on-a-chip. That's a solid argument, but Intel has made this argument too many times before. ARM vendors aren't far behind, either; both TI and Qualcomm have chips coming next year based on an even more efficient 28nm process.

We have to remember Michael Gartenberg's First Law. (Okay, maybe it's his second or third; not so sure of the numbering.) The dean of mobile tech analysts once told me, "never underestimate anyone very rich and very patient." That goes for Microsoft, and it goes for Intel as well.

Indian semiconductor company ships 12 million ICs

Bangalore, India based analog and mixed signal semiconductor chip design company; Cosmic Circuits has shipped 12 Million ICs till November 2011 and expects gross shipments of ASICs to exceed 16 Million ICs by March 2012. This is a good news for Indian ESDM industry, where an Indian company able to ship millions of chips.

Cosmic Circuits says its ICs are used in applications such as tablets, netbooks, cell phones and various other applications. Two main areas of focus are SensorASIC (analog companion chips for sensor applications) and PMASIC (custom power management solutions for portable electronics).

Ganapathy Subramaniam, the CEO of Cosmic Circuits, is projecting his company as one stop solution for all of their analog needs. Cosmic has 5 ICs in production now and expect to have nearly 10 ICs in production by 2012. Cosmic expect to ship more than 25M ICs in 2012 based on forecasts it has received from its customers.
India, where the demand for chips goes in billions both in revenue and shipment, needs Cosmic like companies to balance its trade deficit in electronics hardware.

Its time for VLSI design service companies in India to get into own product development.

Compiling Xilinx library for ModelSim simulator

It was all running cool with VHDL but when i tried to do post Place and Route simulation using SDF file of my design i stuck with following errors:

# ** Error: (vsim-SDF-3250) mips_struct.sdf(18): Failed to find INSTANCE '/top/dut/U1262'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(19): Failed to find INSTANCE '/top/dut/U1262'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(20): Failed to find INSTANCE '/top/dut/U1262'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(21): Failed to find INSTANCE '/top/dut/U1261'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(22): Failed to find INSTANCE '/top/dut/U1261'

googling a lot i found that i need to compile xilinx libraries and had to map it with ModelSim to get it worked. For this u need to write CompXlib in your TCL window of Xilinx.

CompXLib uses the ModelSim "vmap" command for library mapping. If the ModelSim environment variable is set, then the ".ini" file pointed to by the environment variable is modified. If the variable is not set, a local (in the directory in which CompXLib is run) "modelsim.ini" file contains the library mappings from the "vmap" command issued by CompXLib. If the "modelsim.ini" file is not writeable, the "vmap" command will make a local copy of the "modelsim.ini" file and write the library mappings to this file.

I used the “compxlib” command but still it was not working for me. When i checked my modelsim.ini file I found that the libraries was not mapped so i write below command in the modelsim.ini file and finally i find all compiled xilinx libraries in my library window of modelsim.

UNISIMS_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\unisims_ver
UNIMACRO_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\unimacro_ver
UNI9000_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\uni9000_ver
SIMPRIMS_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\simprims_ver
XILINXCORELIB_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\XilinxCoreLib_ver
SECUREIP = C:\Xilinx\10.1\ISE\vhdl\mti_se\secureip
AIM_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\abel_ver\aim_ver
CPLD_VER = C:\Xilinx\10.1\ISE\verilog\mti_se\cpld_ver
UNISIM = C:\Xilinx\10.1\ISE\vhdl\mti_se\unisim
UNIMACRO = C:\Xilinx\10.1\ISE\vhdl\mti_se\unimacro
SIMPRIM = C:\Xilinx\10.1\ISE\vhdl\mti_se\simprim
XILINXCORELIB = C:\Xilinx\10.1\ISE\vhdl\mti_se\XilinxCoreLib
AIM = C:\Xilinx\10.1\ISE\vhdl\mti_se\abel\aim
PLS = C:\Xilinx\10.1\ISE\vhdl\mti_se\abel\pls
CPLD = C:\Xilinx\10.1\ISE\vhdl\mti_se\cpld

** C:\Xilinx\10.1 is path in my system. Please check paths and make changes accordingly.

alternatively you can also use following commands

compxlib -s mti_se -arch virtex -lib unisim -lib simprim -lib xilinxcorelib -l vhdl -dir C:\Mentor\libraries\xilinx\10.1\ISE_Lib\ -log compxlib.log -w
compxlib -s mti_se -arch virtex2p -lib unisim -lib simprim -lib xilinxcorelib -l vhdl -dir C:\Mentor\libraries\xilinx\10.1\ISE_Lib\ -log compxlib.log -w
compxlib -s mti_se -arch virtex4 -lib unisim -lib simprim -lib xilinxcorelib -l vhdl -dir C:\Mentor\libraries\xilinx\10.1\ISE_Lib\ -log compxlib.log -w
compxlib -s mti_se -arch spartan3 -lib unisim -lib simprim -lib xilinxcorelib -l vhdl -dir C:\Mentor\libraries\xilinx\10.1\ISE_Lib\ -log compxlib.log -w
compxlib -s mti_se -arch virtex5 -lib unisim -lib simprim -lib xilinxcorelib -l vhdl -dir C:\Mentor\libraries\xilinx\10.1\ISE_Lib\ -log compxlib.log –w

**(C:\Mentor\libraries\xilinx\10.1\ISE_Lib\  is my path, you can use your own)

List of VLSI Companies

Today India is home to some of the finest semiconductor companies in the world. The semiconductor companies in India are reputed across the globe for their efficient design, verification, validation and manufacturing related solutions for integrated circuits. Also the government of India on approved a plan to construct and equip two wafer fabrication facilities in India, in a move designed to reduce India's reliance on imported semiconductors. Searching a lot we have come across following list of companies that works in VLSI domain. Do write to us if you find any name that needs to be included in this list.

Accel Technologies Limited

Advanced Micro Devices

Alcatel Vacuum Technology (I)

Alliance Semiconductor

Altera Semiconductor (I) Pvt. Ltd.

Australia, China, France, Germany, Japan, Netherlands, Switzerland, USA

Ammos Software Technologies

Analog Alchemy GmbH

Analog Devices Inc

Apache Design Solutions Pvt. Ltd.

Applied Materials


Atheros Communications, Inc.


AustrianMicroSystems (AMS)
Headquartered in Austria-- Semiconductor Foundry

AutoESL Design Technologies

Baegan Technologies

Bartronics (I) Limited

Beceem Communications

Bharat Electronics Limited


Bluespec India

Broadcom Corporation


Calypto Design Systems

Carbon Design Systems
Japan, USA



Chartered Semiconductor Manufacturing Lt
China, German, Japan, Singapore, Taiwan, UK, USA

India, USA

Cir-Q-Tech Tako Technologies Pvt. Ltd.

CircuitSutra Technologies

Cirrus Logic Software
China, Japan, Singapore, South Korea, Taiwan, UK, USA

Cisco Systems Inc

CMR Design Automation Pvt. Ltd.

Conexant Systems, Inc.


Cortina Systems
Canada, China, India, USA

Cortina Systems, Inc.

Cosmic Circuits

CoWare India Pvt. Ltd.

Cranes Software International Limited


Cswitch Canada, Germany, Japan, UK, USA


Dafca Inc.

Denali Software
France, India, Japan, Korea, Singapore, UK, USA

DigiBee Microsystems

Digital Core Design

DSP Group

D\'gipro Systems Pvt. Ltd.

E-Con InfoTech Pvt Ltd

Israel, JAPAN, Singapore, USA

Edison Semiconductors



Embedded Wireless Ltd

Emulex Corporation
India, UK, USA

eon infotech ltd
http:// INDIA

Epcos AG
Brazil, Spain, India, Hungary, Austria (Deutschlandsberg), USA, Czech Republic, Malaysia, Singapore and China.

Esterel EDA Technologies SAS

EVE Design Automation Pvt. Ltd.

Fabtech Technologies International Pvt L

Forte Design Systems


Freescale Semiconductor

GDA Technologies
India, Japan, USA


Genesis Microchip
Canada, China, India, Japan, Korea, Singapore, Taiwan, USA

HCL Technologies

Hellosoft (I) Pvt. Ltd.

Hindustan Semiconductor Manufacturing In

Ibiden Singapore Pte Ltd


Ikanos Communications

Imagination Technologies (I) Private Ltd

Implantaire Technologies (India) Private
Karnataka INDIA

Incide S.A.

Indrion Technologies (I) Pvt. Ltd.

IndusEdge Innovations Pvt. Ltd.

Infineon Technologies


Infinity Infotech Parks Ltd

Ingenient Technologies

India, Japan, Korea, USA

Intel Corporation

Interra Systems (I) Pvt Ltd.

Intersil Analog Service Pvt.Ltd.

Germany, Japan, USA

Ittiam Systems Pvt. Ltd.

iWave Systems Bangalore, Japan

Jeda Technologies
China, USA

kasura Technologies

Kausra technologies INDIA

Kawasaki Microelectronics Inc.

Kilopass Technology Inc.

KLA Tencor Software (I) Pvt. Ltd.

KPIT Cummins Infosystems
France, Germany, India, Japan, Korea, Poland, Singapore, UK, USA

Larsen & Toubro Limited

Lattice Semiconductor Corporation

LIGA Systems USA

Lofru Technologies

Canada, USA

LSI Corporation

Magma Design Automation

Marvell Semiconductor

Masamb Electronics Systems Pvt. Ltd.
Registered Office: A-8, Sector -41, Noida-201303, Uttar pradesh(India)
Corporate Office: G-19, Sector -63, Noida-201301, Uttar pradesh(India)
Phone: +91-120-4541900
Maven Silicon
No.74, 4th Cross, Omkara Nagar, Arekere Mico Layout Main Road, Bannerghatta Road, Bangalore - 560076

Maxim Integrated Products
India, Italy, Netherlands, Philippines, Thailand, Turkey, USA

Mentor Graphics (I) Pvt. Ltd.


Mindspeed Technologies, Inc

MindTree Consulting Ltd.
Australia, Germany, India, Japan, Singapore, Sweden, UAE, United Kingdom, USA

MIPS Technologies
China, Germany, India, Israel, Japan, Taiwan, UK, USA

Mirafra Technologies

Mistral Software
India, Germany, USA

Montalvo Systems
India, USA

MosChip Semiconductor Inc India, USA

Natsem (National Semiconductors)

NEC Electronics Singapore Pvt Ltd

NeoMagic Corporation
India, Israel, USA

NetLogic Microsystems
India, Taiwan, USA

Nevis Networks
China, India, UK, USA

NI Systems (I) Pvt. Ltd.


Israel, UK, USA

Novellus Systems (I) Pvt. Ltd.


Nulife Technology
India, USA

Nvidia Corporation
China, England, Finland, France, Germany, India, Japan, Korea,Russia, Taiwan, USA
NVLogic Technologies Pvt Plt
NVLogic Technologies Pvt. Ltd. 16-2-836/47/B, Road #9, Madhavanagar, Saidabad, Hyderabad - 500 059



PACT XPP Technologies

Patni Computer Systems Limited

Perfectus Technology

India, USA

Philips Semiconductors

Canada, China, India, Israel, USA




India, Taiwan, USA

China, Germany, India, Israel, Japan, South Korea, Netherland, singapore, Taiwan, UK, USA

India, USA

QuickLogic Corporation
Canada, India, USA

Rambus Inc.
Germany, India, Japan, Korea, Taiwan, USA


Stretch Inc. Germany, Japan, USA

SYkio Technologies

Symmid Semiconductor Technology

France, India, Japan, Korea, Taiwan, USA

Synopsys (I) Pvt. Ltd.

Tallika Technologies Pvt Ltd

Tata Consultancy Services Ltd.


India, USA

Tensilica Technologies

India, USA

TES Electronics Soloutions
India, France, Germany, Malaysia, UK, USA

Tessolve Services Pvt. Ltd.

Texas Instruments

Toshiba Embedded Software (India) Pvt Lt

China, India, Israel, Italy, Belgium, France, Germany, Taiwan, UK

TriQuint Semiconductor
China, Costa Rico, Germany, USA

Tundra Semiconductor Corp.
Canada, China, India, Japan, Korea, UK, USA

Japan, Netherlands, Singapore, Taiwan, USA

Velankani Information Systems
India, USA

China, France, Japan, Korea, Taiwan

VinChip Systems Inc

Virage Logic Corporation
Armenia, Germany, India, Israel, Japan, UK, USA



waveaxis technologies

Wipro Technologies


XtremeEDA Corporation

Yogitech SPA

India, Philippines, UK, USA
Zoran Corporation
canada, China, Germany, Israel, Japan, Korea, Taiwan, UK, USA

Pronesis Technologies
Ahmedabad-India, USA

ROHM Semiconductor

SiValley Technologies Pvt. Ltd
email :
Phone:  +91-80 4095 7500

The Brainy CPU - Mimicking the brain, in silicon

What would you say if your smart device started self-learning different languages and became your smart personal translator? What if it had completed a study of quantum mechanics and became your virtual tutor (my wishful thinking to pass a Christmas exam)… :)

CPUFabricated analog very-large-scale integration (VLSI) chip used to mimic neuronal processes involved in memory and learning. (Image: Guy Rachmuth)

MIT researchers have taken this major step by designing a computer chip that mimics how the brain?s neurons perceive new information. This phenomenon is known as ?neuroplasticity? and is an ability of the brain related to learning and memory.

There are about 100 billion neurons in the brain, each of which forms synapses with many other neurons. A synapse is the gap between two neurons (known as the presynaptic and postsynaptic neurons). The presynaptic neuron releases neurotransmitters, such as glutamate and GABA, which bind to receptors on the postsynaptic cell membrane, activating ion channels. Opening and closing those channels changes the cell's electrical potential. If the potential changes dramatically enough, the cell fires an electrical impulse called an action potential.

All of this synaptic activity depends on the ion channels, which control the flow of charged atoms such as sodium, potassium and calcium. Those channels are also key to two processes known as long-term potentiation (LTP) and long-term depression (LTD), which strengthen and weaken synapses, respectively.

A silicon chip can simulate the activity of a single brain synapse - a connection between the presynaptic and postsynaptic neurons relaying information flow - with 400 transistors.

How does the chip work?

In the chip, the transistors could mimic activities of different ion channels. Unlike conventional chips operating in on/off mode (digital), current through the transistors on this new brain chip will flow in analog fashion, driven by a gradient of electrical potential in the same manner of ions flowing through ion channels in a cell. Chi-Sang Poon, a principal research scientist in the Harvard-MIT Division of Health Sciences and Technology, mentioned that it is possible to capture every ionic process going on in a neuron by tweaking the parameters of the circuit to match specific ion channels.

Future applications

There are quite a number of future applications using this brainy chip. It would allow the building of systems to model specific neural functions, such as the visual processing system. Interfacing with biological systems, allowing communication between neural prosthetic devices (e.g. artificial retinas) and the brain would also be possible. The technology would help neuroscientists learn more about how the brain works, and becoming a foundation for artificial intelligence devices. The chip would ultimately lead to a virtual translator and a tutor (I am not giving up on them yet!).


Boolean Algebra Simplified

Once one has defined a notation for an algebra, the rules to manipulate expressions follow. The most simple are the rules that concern the unary operator NOT:

(A')' = A

A • A' = 0

A + A' = 1


General rules like the distributive, commutative, and associative rules hold for the AND and OR binary operators (except one weird one) so that:


A•(B+C) = A•B + A•C

A+(B•C) = (A+B)•(A+C) (the weird one!)



A•B = B•A

A+B = B+A

Associative: (A•B)•C = A•(B•C)

(A+B)+C = A+(B+C)


In addition, there are simplification rules for Boolean equations. There are three important groups of simplification rules.

The first one uses just one variable:

A•A = A

A+A = A


The second group uses Boolean constants 0 and 1:

A • 0 = 0

A • 1 = A

A + 0 = A

A + 1 = 1


The third group involves two or more variables and contains a large number of possible simplification rules (or theorems) such as:


A + A•( B ) = A

( proof: A + A•B = A•(1+B) = A•1 = A )


Note that in this expression either A or B may stand for any complex Boolean expression.

There are two important rules which constitute de Morgan's theorem:

(A+B)' = A' • B'

(A•B)' = A' + B'


This theorem is widely used in Boolean logic design. Stated in words it is: To "invert" (negate) a Boolean expression, you replace the AND operator with the OR operator (or vice versa) and invert the individual terms. The theorem holds for any number of terms, so:


(A+B+C)' = ( (A+B)+C)' = ( (A+B)' )•C' = A'•B'•C'

and similarly:

(A•B•C•....•X)' = A' + B' + C' + ......+ X'


You may have noticed by now that rules are often given in pairs. It makes sense that in a binary system there is some kind of symmetry between the two operators. For Boolean algebra this symmetry is called Duality. Every equation has its dual which one can generate by replacing the AND operators with ORs (and vice versa) and the constants 0 with 1s (and vice versa).


For example, the dual equation of the important simplifying rule:

A + A•B = A


A•(A+B) = A (proof: A•A + A•B = A + A•B = A )


Do not mix up or get confused between a dual expression which is generated by the above rules and the complement (or inverted) expression which is generated by applying the NOT operator. The rules are similar, but they mean very different things.


Finally, let us consider the proposition (I am not taking an umbrella), or:


(U)' = ( C'•(W+R) )'

Apply de Morgan's theorem

U' = (C')' + (W+R)'

Apply de Morgan's theorem again

U' = (C')' + W'•R'

And simplify

U' = C + W'•R'

Comparison Of VHDL and Verilog

There are now two industry standard hardware description languages, VHDL and Verilog. The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison. For example, a designer might have a model of a PCI bus interface written in VHDL, but wants to use it in a design with macros written in Verilog.

VHDL (Very high speed integrated circuit Hardware Description Language) became IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 1076 1993". The Verilog hardware description language has been used far longer than VHDL and has been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in 1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 in December 1995.

There are two aspects to modeling hardware that any hardware description language facilitates; true abstract behavior and hardware structure. This means modeled hardware behavior is not prejudiced by structural or design aspects of hardware intent and that hardware structure is capable of being modeled irrespective of the design's behavior.

VHDL/Verilog compared & contrasted

This section compares and contrasts individual aspects of the two languages; they are listed in alphabetical order.


Hardware structure can be modeled equally effectively in both VHDL and Verilog. When modeling abstract hardware, the capability of VHDL can sometimes only be achieved in Verilog when using the PLI. The choice of which to use is not therefore based solely on technical capability but on:

personal preferences, EDA tool availability, commercial, business and marketing issues

The modeling constructs of VHDL and Verilog cover a slightly different spectrum across the levels of behavioral abstraction; see Figure 1.


  • Figure 1. HDL modeling capability


VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data types

VHDL. A multitude of language or user defined data types can be used. This may m ean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.

Easiest to Learn

Starting with zero knowledge of either language, Verilog is probably the easiest to grasp and understand. This assumes the Verilog compiler directive language for simulation and the PLI language is not included. If these languages are included they can be looked upon as two additional languages that need to be learned. VHDL may seem less intuitive at first for two primary reasons. First, it is very strongly typed; a feature that makes it robust and powerful for the advanced user after a longer learning phase. Second, there are many ways to model the same circuit, specially those with large hierarchical structures.

Forward and back annotation

A spin-off from Verilog is the Standard Delay Format (SDF). This is a general purpose format used to define the timing delays in a circuit. The format provides a bidirectional link between, chip layout tools, and either synthesis or simulation tools, in order to provide more accurate timing representations. The SDF format is now an industry standard in it's own right.

High level constructs

VHDL. There are more constructs and features for high-level modeling in VHDL than there are in Verilog. Abstract data types can be used along with the following statements:

* package statements for model reuse,

* configuration statements for configuring design structure,

* generate statements for replicating structure,

* generic statements for generic models that can be individually characterized, for example, bit width.

All these language statements are useful in synthesizable models.

Verilog. Except for being able to parameterize models by overloading parameter constants, there is no equivalent to the high-level VHDL modeling statements in Verilog.

Language Extensions

The use of language extensions will make a model non standard and most likely not portable across other design tools. However, sometimes they are necessary in order to achieve the desired results.

VHDL. Has an attribute called 'foreign that allows architectures and subprograms to be modeled in another language.

Verilog. The Programming Language Interface (PLI) is an interface mechanism between Verilog models and Verilog software tools. For example, a designer, or more likely, a Verilog tool vendor, can specify user defined tasks or functions in the C programming language, and then call them from the Verilog source description. Use of such tasks or functions make a Verilog model nonstandard and so may not be usable by other Verilog tools. Their use is not recommended.


VHDL. A library is a store for compiled entities, architectures, packages and configurations. Useful for managing multiple design projects.

Verilog. There is no concept of a library in Verilog. This is due to it's origins as an interpretive language.

Low Level Constructs

VHDL. Simple two input logical operators are built into the language, they are: NOT, AND, OR, NAND, NOR, XOR and XNOR. Any timing must be separately specified using the after clause. Separate constructs defined under the VITAL language must be used to define the cell primitives of ASIC and FPGA libraries.

Verilog. The Verilog language was originally developed with gate level modeling in mind, and so has very good constructs for modeling at this level and for modeling the cell primitives of ASIC and FPGA libraries. Examples include User Defined Primitive s (UDP), truth tables and the specify block for specifying timing delays across a module.

Managing large designs

VHDL. Configuration, generate, generic and package statements all help manage large design structures.

Verilog. There are no statements in Verilog that help manage large designs.


The majority of operators are the same between the two languages. Verilog does have very useful unary reduction operators that are not in VHDL. A loop statement can be used in VHDL to perform the same operation as a Verilog unary reduction operator. VHDL has the mod operator that is not found in Verilog.

Parameterizable models

VHDL. A specific bit width model can be instantiated from a generic n-bit model using the generic statement. The generic model will not synthesize until it is instantiated and the value of the generic given.

Verilog. A specific width model can be instantiated from a generic n-bit model using overloaded parameter values. The generic model must have a default parameter value defined. This means two things. In the absence of an overloaded value being specified, it will still synthesize, but will use the specified default parameter value. Also, it does not need to be instantiated with an overloaded parameter value specified, before it will synthesize.

Procedures and tasks

VHDL allows concurrent procedure calls; Verilog does not allow concurrent task calls.


This is more a matter of coding style and experience than language feature. VHDL is a concise and verbose language; its roots are based on Ada. Verilog is more like C because it's constructs are based approximately 50% on C and 50% on Ada. For this reason an existing C programmer may prefer Verilog over VHDL. Although an existing programmer of both C and Ada may find the mix of constructs somewhat confusing at first. Whatever HDL is used, when writing or reading an HDL model to be synthesized it is important to think about hardware intent.

Structural replication

VHDL. The generate statement replicates a number of instances of the same design-unit or some sub part of a design, and connects it appropriately.

Verilog. There is no equivalent to the generate statement in Verilog.

Test harnesses

Designers typically spend about 50% of their time writing synthesizable models and the other 50% writing a test harness to verify the synthesizable models. Test harnesses are not restricted to the synthesizable subset and so are free to use the full potential of the language. VHDL has generic and configuration statements that are useful in test harnesses, that are not found in Verilog.


VHDL. Because VHDL is a very strongly typed language models must be coded precisely with defined and matching data types. This may be considered an advantage or disadvantage. However, it does mean models are often more verbose, and the code often longer, than it's Verilog equivalent.

Verilog. Signals representing objects of different bits widths may be assigned to each other. The signal representing the smaller number of bits is automatically padded out to that of the larger number of bits, and is independent of whether it is the assigned signal or not. Unused bits will be automatically optimized away during the synthesis process. This has the advantage of not needing to model quite so explicitly as in VHDL, but does mean unintended modeling errors will not be identified by an analyzer.

Designing RTL hardware models in VHDL and Verilog

The models have additional inputs and outputs over and above that of the algorithmic models. They are inputs Clock, Reset_N and Load, and the output Done. When Load is at logic 1 it signifies input data is available on inputs A and B, and are loaded into separate registers whose output signals are called A_hold and B_ hold. The extra output signal, Done, switches to a logic 1 to signify the greate st common divisor has been computed. It takes a number of clock cycles to comput e the GCD and is dependent upon the values of A and B.

The models are broken down into three process (VHDL)/always (Verilog) statements.

First process/always statement LOAD_SWAP. Infers two registers which operate as follows:

1) When Reset_N is at a logic 0, A_hold and B_hold are set to zero.

2) When not 1) and Load is at logic 1, data on A and B is loaded into A_hold and B_hold.

3) When not 1) or 2) and A_hold is less than B_hold, values on A_hold and B_hold are swapped, that is, A_hold and B_hold are loaded into B_hold and A_hold respectively.

4) When not 1), 2) or 3), A_hold is reloaded, that is, it keeps the same value. The value of A_hold - B_hold, from the second process/always statement, is loaded into B_hold.

Second process/always statement SUBTRACT_TEST. The first if statement tests to see if A_hold is greater than or equal to B_hold. If it is, the subtraction, A_hold - B_hold, occurs and the result assigned to A_New ready to be loaded into B_hold on the next rising edge of the clock signal. If A_hold is less than B_hold, then subtraction cannot occur and A_New is assigned the value B_hold so that a swap occurs after the next rising edge of the clock signal. The second if statement checks to see if the value of B_hold has reached zero. If it has, signal Done is set to logic 1 and the value of A_ hold is passed to the output Y through an inferred multiplexer function.

It is a requirement of the problem to synthesize the generic model with 8-bit bus signals. This is easily achieved in Verilog model by setting the default parameter value Width to 8. This means it does not need to be separately instantiat ed before it can be synthesized and have the correct bit width. This is not the case in VHDL, which uses a generic. The value of the generic is only specified when the model is instantiated. Although the VHDL model will be instantiated in the test harness, the test harness is not synthesized. Therefore, in order to synthesize an 8-bit GCD circuit a separate synthesizable model must be used to instantiate the RTL level model which specifies the generic, Width, to be 8. The simulation test harness does not need to use this extra model as it too, will specify the generic, Width, to be 8.

VHDL RTL model
library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;
entity GCD is
generic (Width: natural);
port (Clock,Reset,Load: in std_logic;
   A,B:   in unsigned(Width-1 downto 0);
   Done:  out std_logic;
   Y:     out unsigned(Width-1 downto 0));
end entity GCD;
architecture RTL of GCD is
   signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0);
   signal A_lessthan_B: std_logic;
-- Load 2 input registers and ensure B_Hold < A_Hold
LOAD_SWAP: process (Clock)
   if rising_edge(Clock) then
     if (Reset = '0') then
       A_Hold <= (others => '0');
       B_Hold <= (others => '0');
     elsif (Load = '1') then
       A_Hold <= A;
       B_Hold <= B;
     else if (A_lessthan_B = '1') then
       A_Hold <= B_Hold;
       B_Hold <= A_New;
     else A_Hold <= A _New;
     end if;
   end if;
end process LOAD_SWAP;
SUBTRACT_TEST: process (A_Hold, B_Hold)
   -- Subtract B_Hold from A_Hold if A_Hold >= B_Hold
   if (A_Hold >= B_Hold) then
      A_lessthan_B <= '0';
      A_New <= A_Hold - B_Hold;
      A_lessthan_B <= '1';
      A_New <= A_Hold;
   end if;
   -- Greatest common divisor found if B_Hold = 0
   if (B_Hold = (others => '0')) then
      Done <= '1';
      Y <= A_Hold;
      Done <= '0';
      Y <= (others => '0');
   end if;
end process SUBTRACT_TEST;
end architecture RTL;
Verilog RTL model
module GCD (Clock, Reset, Load, A, B, Done, Y);
parameter Width = 8;
input Clock, Reset, Load;
input [Width-1:0] A, B;
output Done;
output [Width-1:0] Y;
reg A_lessthan_B, Done;
reg [Width-1:0] A_New, A_Hold, B_Hold, Y;
// Load 2 input registers and ensure B_Hold < A_Hold
always @(posedge Clock)
    begin: LOAD_SWAP
       if (Reset) begin
           A_Hold = 0;
           B_Hold = 0;
       else if (Load) begin
           A_Hold = A;
           B_Hold = B;
       else if (A_lessthan_B) begin
           A_Hold = B_Hold;
           B_Hold = A_New;
           A_Hold = A_New;
always @(A_Hold or B_Hold)
      // Subtract B_Hold from A_Hold if A_Hold >= B_Hold
      if (A_Hold >= B_Hold) begin
         A_lessthan_ B = 0;
         A_New = A_Hold - B_Hold;
      else begin
         A_lessthan_B = 1;
         A_New = A_Hold;
      // Greatest common divisor found if B_Hold = 0
      if (B_Hold == 0) begin
         Done = 1;
         Y = A_Hold;
      else begin
         Done = 0;
         Y = 0;



The reasons for the importance of being able to model hardware in both VHDL and Verilog has been discussed. VHDL and Verilog has been extensively compared and contrasted in a neutral manner.

Finite State Machine (FSM) Coding In Verilog

There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states.
Verilog Code for FSM:
// 4-State Moore state machine
// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes.  (State
// transitions are synchronous.)
module seq_dect
    input    clk, data_in, reset,
    output reg  data_out
    // Declare state register
    reg        [2:0]state;
    // Declare states
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;

    // Determine the next state
    always @ (posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
            case (state)
                    if (data_in)
                        state <= S1;
                        state <= S0;
                    if (data_in)
                        state <= S1;
                        state <= S2;
                    if (data_in)
                        state <= S3;
                        state <= S2;
                    if (data_in)
                        state <= S4;
                        state <= S2;
                    if (data_in)
                        state <= S1;
                        state <= S2;
            endcase // case (state)
    end // always @ (posedge clk or posedge reset)
    // Output depends only on the state
    always @ (state) begin
        case (state)
                data_out = 1'b0;
                data_out = 1'b1;
                data_out = 1'b0;
                data_out = 1'b1;
                data_out = 1'b1;               
                data_out = 1'b0;
        endcase // case (state)
    end // always @ (state)

endmodule // moore_mac

Finite State Machine (FSM) Coding In VHDL

There is a special Coding style for State Machines in VHDL as well as in Verilog.
Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states.
 VHDL Code for FSM:
library IEEE;
--Sequence detector for detecting the sequence "1011".
--Overlapping type.
entity seq_det is
port(   clk   : in std_logic;      --clock signal
        reset : in std_logic;      --reset signal
        S_in  : in std_logic;      --serial bit Input sequence   
        S_out : out std_logic);    -- Output        
end seq_det;
architecture Behavioral of seq_det is
--Defines the type for states in the state machine
type state_type is (S0,S1,S2,S3,S4);
--Declare the signal with the corresponding state type.
signal Current_State, Next_State : state_type;
-- Synchronous Process
    if( reset = '1' ) then                 --Synchronous Reset
        Current_State <= 'S0';
    elsif (clk'event and clk = '1') then   --Rising edge of Clock
        Current_State <= Next_State
    end if;
end process;
-- Combinational Process
Process(Current_State, S_in)
        case Current_State is
            when S0 =>                     
                S_out <= '0';
                if ( s_in = '0' ) then
                    Next_State <= S0;
                    Next_State <= S1;
                end if;
            when S1 =>
                S_out <= '1';  
                if ( S_in = '0' ) then
                    Next_State <= S3;
                    Next_State <= S2;
                end if;
            when S2 =>
                S_out <= '0';  
                if ( S_in = '0' ) then
                    Next_State <= S0;
                    Next_State <= S3;
                end if;
            when S3 =>
                S_out <= '1';  
                if (S_in = '0' ) then
                    Next_State <= S2;
                    Next_State <= S4;
                end if;
            when S4 =>
                S_out <= '1';  
                if ( S_in = '0' ) then
                    Next_State <= S2;
                    Next_State <= S1;
                end if;
            when others =>
        end case;
    end if;
end process;   

Verilog Design With VHDL Testbench

// Two bit adder design in Verilog

module adder (a,b,carry,sum);
   //Port Declarations
   input [1:0] a;
   input [1:0] b;
   output [1:0] sum;
   output  carry;
   //Drivers for output signals
   reg [1:0]  sum;
   reg   carry;  
   // combination Logic for adder
   always @ (a or b) //Sensitive to inputs a or b
         {carry,sum} = a+b; 


--VHDL test bench for Verilog adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ADDER_TB is      --Top level entity dosen't have any port

architecture TB of ADDER_TB is

    component ADDER is
    port( A: in std_logic_vector(1 downto 0);
  B: in std_logic_vector(1 downto 0); 
  carry: out std_logic;     
  sum: out std_logic_vector(1 downto 0)
    end component;

    signal A, B: std_logic_vector(1 downto 0);
    signal carry: std_logic;
    signal sum:  std_logic_vector(1 downto 0);

        DUT: ADDER port map (A, B, carry, sum);
variable err_cnt: integer :=0;
    begin -- Generating test vectors
-- case 1
A <= "00";      
B <= "00";
wait for 10 ns;
assert (sum="00") report "Sum Error!" severity error;
assert (carry='0') report "Carry Error!" severity error;
if (sum/="00" or carry/='0') then
end if;
  -- case 2  
A <= "11";
B <= "11";
wait for 10 ns;  
assert (sum="10") report "Sum Error!" severity error; 
assert (carry='1') report "Carry Error!" severity error;
if (sum/="10" or carry/='1') then
end if;
-- case 3
A <= "01";
B <= "10";
wait for 10 ns;  
assert (sum="11") report "Sum Error!" severity error; 
assert (carry='0') report "Carry Error!" severity error;
if (sum/="11" or carry/='0') then
end if;
-- case 4
A <= "10";
B <= "01";
wait for 10 ns;   
assert (sum="11") report "Sum Error!" severity error; 
assert (carry='0') report "Carry Error!" severity error;
if (sum/="11" or carry/='0') then
end if;
-- case 5
A <= "01";
B <= "01";
wait for 10 ns;
assert (sum="10") report "Sum Error!" severity error;
assert (carry='0') report "Carry Error!" severity error;
if (sum/="10" or carry/='0') then
end if;
-- summary of testbench
if (err_cnt=0) then
     assert false
     report "Test completed successfully for adder!"
     severity note;
     assert true
     report "ERROR - Expected and received results are wrong"
     severity error;
end if;
    end process;
end TB;

VHDL Design With Verilog Testbench

--VHDL Design for 4:1 multiplexor

library ieee;
use ieee.std_logic_1164.all;
entity Mux is
  port(I3  : in  std_logic_vector(2 downto 0);
        I2 : in  std_logic_vector(2 downto 0);
        I1 : in  std_logic_vector(2 downto 0);
        I0 : in  std_logic_vector(2 downto 0);
        S  : in  std_logic_vector(1 downto 0);
        O  : out std_logic_vector(2 downto 0)
end Mux;
architecture behv1 of Mux is
  process(I3, I2, I1, I0, S)
    -- use case statement
    case S is
      when "00"   => O <= I0;
      when "01"   => O <= I1;
      when "10"   => O <= I2;
      when "11"   => O <= I3;
      when others => O <= "ZZZ";
    end case;
  end process;
end behv1;


//Verilog Test Bench for 4:1 VHDL multiplexer

module mux_tb (i3,i2,i1,i0,s,o);
   input  [2:0] o;
   output [2:0] i3;
   output [2:0] i2;
   output [2:0] i1;
   output [2:0] i0;
   output [1:0]  s;
   //Drivers for output
   reg [2:0] i3;
   reg [2:0] i2;
   reg [2:0] i1;
   reg [2:0] i0;
   reg [1:0] s;
   //Error counter
   integer   error_count;
   //Generatiin test cases
error_count = 0;
//Assigning different values for different signals
i3 = 3'h4;
i2 = 3'h7;
i1 = 3'h0;
i0 = 3'h5;
s  = 2'b00;
#2 //wait for 2 delays
if (o != 3'h5)
      $display("Error in case 1\n");
      error_count = error_count + 1;     
s  = 2'b01;
#2 //wait for 2 delays
if (o != 3'h0)
      $display("Error in case 2\n");
      error_count = error_count + 1;     
s  = 2'b10;
#2 //wait for 2 delay
if (o != 3'h7)
      $display("Error in case 3\n");
      error_count = error_count + 1;     
s  = 2'b11;
#2 //wait for 2 delay
if (o != 3'h4)
      $display("Error in case 4\n");
      error_count = error_count + 1;     
//Test Summary
   $display("ERROR in the design");
   $display("All test cases are passed");
//mux instantiation and port mapping
   mux one(.i3(i3),.i2(i2),.i1(i1),.i0(i0),.s(s),.o(o));

Mixed Language Simulation In VLSI

Most of Simulation Tools supports mixed language project files and mixed language simulation. This enables you to include Verilog modules in a VHDL design, and vice versa. Some restrictions do apply:

  • Mixing VHDL and Verilog is restricted to the module instance or component only. A VHDL design can instantiate Verilog modules and a Verilog design can instantiate VHDL components. Any other kind of mixing between VHDL and Verilog is not supported.
  • A Verilog hierarchical reference cannot refer to a VHDL unit nor can a VHDL expanded/selected name refer to a Verilog unit.
  • Only a small subset of VHDL types, generics and ports are allowed on the boundary to a Verilog module. Similarly, a small subset of Verilog types, parameters and ports are allowed on the boundary to VHDL design unit.
  • Component instantiation-based default binding is used for binding a Verilog module to a VHDL design unit. Specifically, configuration specification, direct instantiation and component configurations are not supported for a Verilog module instantiated inside a VHDL design unit.


1. VHDL Design With Verilog Testbench

2. Verilog Design With VHDL Testbench

Verilog Always Block

Contains one or more statements (procedural assignments, task enables, if, case and loop statements), which are executed repeatedly throughout a simulation run, as directed by their timing controls.





Where to use:

Rules for Using always Statement:
Only registers (reg, integer, real, time, realtime) may be assigned in an

Every always starts executing at the start of simulation, and continues executing throughout simulation; when the last statement in the always is reached, execution continues from the top of the always.

  • An always containing more than one statement must enclose the statements in a begin-end or fork-join block.
  • An always with no timing controls will loop forever.

always is one of the most useful Verilog statements for synthesis, yet an always is often unsynthesizable. For best results, code should be restricted to one of the following templates:

always @(Inputs) // All the inputs
... // Combinational logic

always @(Inputs) // All the inputs
if (Enable)
... // Latched actions

always @(posedge Clock) // Clock only
... // Synchronous actions

always @(posedge Clock or negedge Reset)
// Clock and Reset only
if (!Reset) // Test active level of asynchronous reset
... // Asynchronous actions
... // Synchronous actions
end // Gives flipflops + logic

Cyclic Redundancy Checking (CRC)

Error detection is an important part of communication systems when there is a chance of data getting corrupted. Whether it’s a piece of stored code or a data transmission, you can add a piece of redundant information to validate the data and protect it against corruption. Cyclic redundancy checking is a robust error-checking algorithm, which is commonly used to detect errors either in data transmission or data storage. In this multipart article we explain a few basic principles.

Modulo two arithmetic is simple single-bit binary arithmetic with all carries or borrows ignored. Each digit is considered independently. This article talks about how modulo two addition is equivalent to modulo two subtraction, and can be performed using an exclusive OR operation followed by a brief on Polynomial division where remainder forms the CRC checksum.
For example, we can add two binary numbers X and Y as follows:

10101001 (X) + 00111010 (Y) = 10010011 (Z)

From this example the modulo two addition is equivalent to an exclusive OR operation. What is less obvious is that modulo two subtraction gives the same results as an addition.
From the previous example let’s add X and Z:

10101001 (X) + 10010011 (Z) = 00111010 (Y)

In our previous example we have seen how X + Y = Z therefore Y = Z – X, but the example above shows that Z+X = Y also, hence modulo two addition is equivalent to modulo two subtraction, and can be performed using an exclusive OR operation.

In integer division dividing A by B will result in a quotient Q, and a remainder R. Polynomial division is similar except that when A and B are polynomials, the remainder is a polynomial, whose degree is less than B.

The key point here is that any change to the polynomial A causes a change to the remainder R. This behavior forms the basis of the cyclic redundancy checking.
If we consider a polynomial, whose coefficients are zeros and ones (modulo two), this polynomial can be easily represented by its coefficients as binary powers of two.

In terms of cyclic redundancy calculations, the polynomial A would be the binary message string or data and polynomial B would be the generator polynomial. The remainder R would be the cyclic redundancy checksum. If the data changed or became corrupt, then a different remainder would be calculated.

Although the algorithm for cyclic redundancy calculations looks complicated, it only involves shifting and exclusive OR operations. Using modulo two arithmetic, division is just a shift operation and subtraction is an exclusive OR operation.

Cyclic redundancy calculations can therefore be efficiently implemented in hardware, using a shift register modified with XOR gates. The shift register should have the same number of bits as the degree of the generator polynomial and an XOR gate at each bit, where the generator polynomial coefficient is one.

Augmentation is a technique used to produce a null CRC result, while preserving both the original data and the CRC checksum. In communication systems using cyclic redundancy checking, it would be desirable to obtain a null CRC result for each transmission, as the simplified verification will help to speed up the data handling.

Traditionally, a null CRC result is generated by adding the cyclic redundancy checksum to the data, and calculating the CRC on the new data. While this simplifies the verification, it has the unfortunate side effect of changing the data. Any node receiving the data+CRC result will be able to verify that no corruption has occurred, but will be unable to extract the original data, because the checksum is not known. This can be overcome by transmitting the checksum along with the modified data, but any data-handling advantage gained in the verification process is offset by the additional steps needed to recover the original data.

Augmentation allows the data to be transmitted along with its checksum, and still obtain a null CRC result. As explained before when obtain a null CRC result, the data changes, when the checksum is added. Augmentation avoids this by shifting the data left or augmenting it with a number of zeros, equivalent to the degree of the generator polynomial. When the CRC result for the shifted data is added, both the original data and the checksum are preserved.

In this example, our generator polynomial (x3 + x2 + 1 or 1101) is of degree 3, so the data (0xD6B5) is shifted to the left by three places or augmented by three zeros.

0xD6B5 = 1101011010110101 becomes 0x6B5A8 = 1101011010110101000.

Note that the original data is still present within the augmented data.
0x6B5A8 = 1101011010110101000
Data = D6B5 Augmentation = 000

Calculating the CRC result for the augmented data (0x6B5A8) using our generator polynomial (1101), gives a remainder of 101 (degree 2). If we add this to the augmented data, we get:

0x6B5A8 + 0b101 = 1101011010110101000 + 101
= 1101011010110101101
= 0x6B5AD

As discussed before, calculating the cyclic redundancy checksum for 0x6B5AD will result in a null checksum, simplifying the verification. What is less apparent is that the original data is still preserved intact.

0x6B5AD = 1101011010110101101
Data = D6B5 CRC = 101

The degree of the remainder or cyclic redundancy checksum is always less than the degree of the generator polynomial. By augmenting the data with a number of zeros equivalent to the degree of the generator polynomial, we ensure that the addition of the checksum does not affect the augmented data.

In any communications system using cyclic redundancy checking, the same generator polynomial will be used by both transmitting and receiving nodes to generate checksums and verify data. As the receiving node knows the degree of the generator polynomial, it is a simple task for it to verify the transmission by calculating the checksum and testing for zero, and then extract the data by discarding the last three bits.

Thus augmentation preserves the data, while allowing a null cyclic redundancy checksum for faster verification and data handling.

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