Featured post

Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Saturday, 3 April 2010

What is Clock Skew?

Given two sequentially-adjacent registers, Ri and Rj, and an equipotential clock distribution network, the clock skew between these two registers is defined as




Tskew-i,j = Tci - Tcj



where Tci and Tcj are the clock delays from the clock source to the registers Ri and Rj, respectively.



No comments:

Post a comment

Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.