Netgen - The Circuit Netlist Comparison (LVS) and Netlist Conversion Tool

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Netgen version 1.3 is the stable branch and has been essentially unchanged for several years. The development branch version 1.4 is an attempt to bring netgen up to par with the industry-standard Calibre tool from Mentor Graphics. Since (as far as I know) all LVS tools are based on the same class partitioning algorithm, this effort is not as difficult as it may seem. Mostly, netgen must be made to properly understand hierarchy, device properties, and generate a more readable output. All these changes are now underway (as of November 2007, when the development version 1.4 branch was created).

Netgen was developed independently of magic, written by Massimo Sivilotti, and eventually incorporated into the beginnings of the Tanner L-Edit suite of tools. However, the original code was left open source, and so I have incorporated it into the Tcl-based suite of tools including magic, IRSIM, and xcircuit.

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